[SI-LIST] Re: Stimulus dilemma for pwr/gnd model
- From: Sandy Taylor <cmos@xxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 07 May 2007 11:42:15 -0700
Agathon
I think you are on the right track with your assumptions. Here are a few
thoughts:
1) Be sure to estimate the package die resonant frequency, and the
damping effects built into
the power/gnd distribution. With low resistance copper on die power
distribution and a
"good" package, it is possible to get Q > 1. I can send you some sample
data on that privately
if you are interested.
2) Consider modeling the device load as a set of time varying resistors,
rather than ideal
PWL current sources. Since you are looking at inductive (and resonant
effects),
using a current source (with infinite parallel resistance) would
exaggerate the resonant effects.
Larry Smith published a paper on this: "Chip-Package resonance in Core
Power Supply Structures
for a High Power Microprocessor." Remember the lower the supply
distribution series resistance,
the higher the Q.
3) If the IO power is significant, it should be handled with different
assumptions than the core power.
In most designs, the IO activity characteristics is very different from
the core, with vss shared,
and separate vdd/vddio supplies. Every part is different, but the
interaction is usually
significant enough that it should be taken into account.
4) I'm not exactly sure what you meant by "Worst case stimulus
(guaranteed to be unrealistic)",
but if you mean switching everything at once, then yes. Depending on the
simulator(s) you
are using, you can probably get nodal activity statistics on a vector by
vector basis. This can be
used to select the highest current and highest change in current
vectors. Ideally you would take
the individual node capacitance and voltage swing into account, but the
team I worked with
on this found that simple toggle counts were very accurate in
identifying "vectors of interest."
Once you have identified vectors of interest you can invest the effort
as you described
in a more detailed simulation.
5) For the chips I have seen for at least the past decade, the I(t)
peaks within a clock cycle
are primarily handled by the intentional on chip decaps, and other
sources of on chip decoupling
(wells, non-switching signals etc.) I bring this up because of your
point #3. The exact timing
and shape of the current waveform within a clock cycle ... within the
bounds of reason
(and yes, some people out there are successfully pushing the bounds of
reason)
The package is usually a pretty effective low pass filter compared to
the clock rate.
Maybe I'm reading too much into your third point. But if you have an
estimate of the average
current, and you look at the high vs low activity, you can come up with
a pretty decent
time varying resistor to model the load.
I hope this helps,
Sandy Taylor
CMOS Solutions
Olga, WA
agathon wrote:
> Hello all,
> Once I have some kind of assumed good system model for a power rail, ideally
> I'd like to have already finished an extraction of I vs. t for worst case
> pwr bump of the chip -- from simulation using a best-accuracy tool. Later
> on, in an ideal world where time, etc., are cheap I'd like a bare-die
> profile of the same, gotten from measurements -- for each worst case pwr
> bump.
>
> I'd use this as behavioral current stimulus for my PDN in simulations.
> Specifically, the I vs. t for peak would be for peak CHANGES in I --- that
> is, from chip's state changes that produce the largest swing in I and slew
> rate. With no credible stimulus, all the SI tool time is useless for pwr
> integrity.
>
> My question:
> The above two ways to generate such stimulus are actually damn costly,
> especially if decision makers aren't forward looking and there's no time to
> go back & do it "right".
> Yet I can get SI tools as part of the normal course and generate the pwr
> models.
>
> Next best thing: turn the problem around .....
> 1. invent [I vs. t] stimulus based on estimates from real chip sim data &
> models
> 2. find the worst case stimulus (guaranteed to be unrealistic)
> 3. yet, this will find the worst case swing (peak & slew rate cases), though
> time scale will be a total WAG (a guess) ---> may still have some value
>
>
> Any thoughts...?
>
>
> -Agathon
>
>
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