[SI-LIST] Re: Stackup for insertion loss control ownership
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: <jeff.loyer@xxxxxxxxx>, <Gert.Havermann@xxxxxxxxxxx>, "SI-List" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 8 Jan 2013 08:35:39 -0800
Hi,
There is a hybrid solution that we use for stackups:
1. Specify overall requirements (like you do Jeff)
2. request detailed stackup document from PCB vendor
3. review it, and if that does not have the parameters we would have chosen,
then request a modification
4. After modified agree in the stackup and "fix" it, so they cannot change
it later without our engineer's review.
Basically we dont micro-specify just micro-review all parameters of the
stackup.
This way the PCB fab chooses the parameters as it is the best for their
stock/process, and it should not be too expensive. I worked a few companies,
and we always done it this way.
regards,
Istvan Nagy
Fortinet, Sunnyvale CA
-----Original Message-----
From: Loyer, Jeff
Sent: Tuesday, January 08, 2013 7:52 AM
To: Gert.Havermann@xxxxxxxxxxx ; SI-List
Subject: [SI-LIST] Stackup for insertion loss control ownership
Hello Gert,
I changed the "Subject" to better reflect what I believe we're currently
discussing.
The speeds I'm dealing with are significantly greater than 5G. The
question, to me, isn't what particulars you have to manage, but who should
be managing them. There are some, like yourself, who believe the SI
engineer should manage all the details of the stackup. There are others
(me) who believe it is best to drive the PCB vendors to satisfy the
impedance and insertion loss requirements. Here are some of the reasons I
feel this way:
1, 2, & 3) Cost, cost, cost. The more constraints I place on my PCB
vendor(s), the more I pay. Frankly, I don't understand how folks who so
tightly constrain their designs get around this. As I said earlier, I
believe that is because we are operating under very different paradigms;
cost is a major factor in my designs and thus I need to give my PCB vendors
all the leeway I can while still meeting my impedance and insertion loss
requirements.
4) I don't want to be responsible for the mechanical aspects of the design.
I haven't heard anyone mention any mechanical aspects of the various
materials and/or foil types in this forum and doubt that is because there
aren't any. I believe it is because that is not our forte, and I don't want
it to become mine. I would rather the PCB vendor make intelligent/informed
decisions with knowledge about electrical and mechanical properties.
5) As with impedance control, I believe that the PCB vendor has more insight
into critical factors than I do and thus is in a better position to make the
best decision to balance all the requirements to attain the best design.
6) As I said earlier, I can make it a career handling nothing but stackups
for a sophisticated server design if I own all the details.
All this hinges on the assumption that the PCB vendor is knowledgeable about
insertion loss. At this point, I believe that if you mention an insertion
loss requirement and you get a blank stare, you should go elsewhere. If
instead they offer to measure and control insertion loss, you can probably
assume they've already done some internal work and can offer
intelligent/informed recommendations to meet your needs at a competitive
price.
On a similar/related note, I believe most vendors are aware of the
Fiberweave Effect and the use of spread glass to mitigate it. If that is
your choice to mitigate for it, I believe that is best done as a
requirement, not by specifying a very particular glass style.
Cheers,
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Havermann, Gert
Sent: Monday, January 07, 2013 11:59 PM
To: SI-List
Subject: [SI-LIST] AW: Re: AW: Re: AW: AW: Asymmetric differential stripline
impedance
Jeff,
Especially in these cases micro managing up to some extend is important. If
you have to mix different glass styles (e.g. 106 and 1080) And you do not
specify which has to be put closer to the signal layer, then you will most
propably get different performance from different PCB vendors, and maybe
even from the same vendor if just pots in the prepregs in mixed order. The
effective dk the diff pair sees will differ by stackup, and the weave effect
will differ too, thus this effects impedance, ILD and timing.
For speeds exceeding 5G I would never leave this details unspecified.
You are right that for low speeds this doesn't have to be an issue, but it
seems to me that speeds are increasing rapidly everywhere.
BR
Gert
----------------------------------------
Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.: HRB
8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm. Edgar-Peter Düning,
Dipl.-Ing. Torsten Ratzmann, Dr.-Ing. Alexander Rost
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Loyer, Jeff
Gesendet: Montag, 7. Januar 2013 19:38
An: Lee ; SI-List
Betreff: [SI-LIST] Re: AW: Re: AW: AW: Asymmetric differential stripline
impedance
Yes, PCIeG2 has these speeds. Again, the approach taken may depend on the
situation. If you don't have the luxury of using spread glass, you may be
forced to use other mitigation techniques as described in our DesignCon
paper "Fiber Weave Effect: Practical Impact Analysis and Mitigation
Strategies".
Jeff Loyer
-----Original Message-----
From: Lee [mailto:leeritchey@xxxxxxxxxxxxx]
Sent: Monday, January 07, 2013 9:33 AM
To: Loyer, Jeff; Gert.Havermann@xxxxxxxxxxx; SI-List
Subject: Re: [SI-LIST] Re: AW: Re: AW: AW: Asymmetric differential stripline
impedance
When you have 5 Gb/S differential pairs, weave type makes all the difference
in the world. I think that PCI Express has speeds like this now. Most any
Internet switch or router does as well.
-----Original Message-----
From: Loyer, Jeff
Sent: Monday, January 07, 2013 9:00 AM
To: Gert.Havermann@xxxxxxxxxxx ; SI-List
Subject: [SI-LIST] Re: AW: Re: AW: AW: Asymmetric differential stripline
impedance
Sorry Gert for the confusion my posting may have invoked. Yes, I only meant
to imply alignment regarding accuracy of field solvers.
It sounds like you and Lee take a different approach than me, specifying
many more particulars than I normally would. I think I can help clarify
that disconnect between our approaches...
If I am designing a super-high performance design which is pushing the
absolute limits of current technology, I would probably take the approach of
micro-managing every aspect of the stackup, as you and Lee (and others)
prescribe.
If my design isn't pushing far past the envelope of "standard practice"
and/or is very cost conscious, that approach is not practical. For
instance, I may be designing a server with as many as 6 or 7 PCB's in that
design, and each of those must have 2 or 3 possible vendors. Micro-managing
the stackup of each of those 14-21 unique designs would consume an
Engineer's entire time. That is the market I am typically involved in, thus
I feel more pressure to drive the PCB vendors to develop the tools and
knowledge necessary to allow me to merely specify an impedance and insertion
loss spec. and have the PCB vendors meet those requirements. This way they
are also responsible for elements I can't own - mechanical reliability,
expansion coefficients, assembly issues, etc.
I hope this helps clarify the seemingly disparate methodologies.
Also, Scott M. responded off-line about the inherent flaws in our current
impedance measurement techniques which add another fly to the ointment, and
I agree wholeheartedly that there is a need for revision here. I've seen
some very promising work, extrapolating back to the launch point, though I
don't recall off-hand who the authors were.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Havermann, Gert
Sent: Monday, January 07, 2013 8:14 AM
To: SI-List
Subject: [SI-LIST] AW: Re: AW: AW: Asymmetric differential stripline
impedance
Just to make myself clear:
When I said: "The Processing has so much influence, that I usually just push
my PCB maker as far as I can to a point where he simply can't mess up my
design, and then I give him the freedom to implement his processing
tolerances."
I meant that I specify everything needed to meet the desired performance
(that's exact prepreg style, glass style, material, copper roughness,
copperweight, laminate and prepreg position in the stack, layer
registration). That's much more than just what's needed for impedance, but
well enough that the PCB maker can't vary things that would influence the
performance. The only thing he needs to do is to match the etching
tolerances with his pressing tolerances to meet the impedance.
Knowing that the etch might be adjusted is important as I have to use loose
enough coupling to allow for modifications (if diff pair spacing is already
at the producible limit, this wouldn't work out).
And especially for "beginners" it is the better choice to let the PCB maker
take care about the impedance, and learn from his feedback and from
literature to become an SI-PBC expert.
BR
Gert
----------------------------------------
Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.: HRB
8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm. Edgar-Peter Düning,
Dipl.-Ing. Torsten Ratzmann, Dr.-Ing. Alexander Rost
-----Ursprüngliche Nachricht-----
Von: Loyer, Jeff [mailto:jeff.loyer@xxxxxxxxx]
Gesendet: Montag, 7. Januar 2013 16:55
An: leeritchey@xxxxxxxxxxxxx; Havermann, Gert; SI-List
Betreff: RE: [SI-LIST] Re: AW: AW: Asymmetric differential stripline
impedance
As I've posted in this forum before, I'm more in Gert's camp. The best you
can do, in my experience, is to get close to the target impedance and allow
your manufacturer to make small (<0.5mil is my rule of thumb) changes in
trace dimensions and/or dielectric thicknesses to meet the impedance spec.
What I typically find is that most vendors approximately match my impedance
estimate within those limits. Those that don't usually have a fundamental
flaw in their modeling assumptions (incorrect assumption about whether the
top dielectric thickness is from the top or bottom of the trace, different
Er assumption, etc.), not an inaccurate modeling tool.
As Gert said, to get more precise correlation you would need information
from cross-sectioning actual traces after they've been built. If this tool
gets within a couple of ohms in most cases, that would probably be
sufficient for many cases.
To me, this is a separate issue than whether I specify a particular glass
style or copper finish, and I'd like have them (the fab shops) own these in
an intelligent/informed fashion also.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Lee
Sent: Friday, January 04, 2013 10:07 AM
To: Gert.Havermann@xxxxxxxxxxx; SI-List
Subject: [SI-LIST] Re: AW: AW: Asymmetric differential stripline impedance
That's the way we have done this work for quite a while- let the fab shop
design the final stackup. Unfortunately, there is far more to designing a
stackup than just impedance, such as glass style, copper finish, etc. Most
of these, if not all are out of the scope of a fab shop's skill set. For
this reason, most of use have no choice but to take charge of the impedance
calculation as opposed to putting the burden on the fab shop. It was always
our job anyway! We just got away with forcing the fab shop to do it.
For these reasons, it is necessary to get impedance right before sending the
stackup off to a fab shop. That is why I argue for field solver based
calculators and good laminate data.
-----Original Message-----
From: Havermann, Gert
Sent: Friday, January 04, 2013 8:57 AM
To: Lee ; SI-List
Subject: [SI-LIST] AW: AW: Asymmetric differential stripline impedance
Lee,
I use it to find a starting point for 3D simulations. It can't be accurate
as one can not calculate with different prepreg styles or other real world
problems. But besides that its not a bad tool.
I think the biggest error in the end is the implementation of the design,
and there even 3D simulation doesn't help you if you don't know how PCBs are
made and which are the Materials used (not only electrical models, but also
processing related like flow behavior during pressing, copper fill of the
layer...). You know what I'm talking about.
If I have all the knowledge, then I take those parameters into my
calculation and do a 3D simulation of the right offset and the correct
GND-GND distance and correct material and surface roughness... And then I
know that the impedance will be at least close to where I wanted it to be.
For others without this detail of knowledge of PCB Fab and Materials, This
tool is a good starting point for their design. Then you hand this design to
a pcb vendor with knowledge in Impedance manufacturing and let him do the
fine tuning of the trace based on his experience to meet +/-10% impedance
match. If The vendor fails, he looses money, and you loose time, but with
the right partner it works great even at higher speeds.
The Processing has so much influence, that I usually just push my PCB maker
as far as I can to a point where he simply can't mess up my design, and then
I give him the freedom to implement his processing tolerances.
And quite frankly, if someone here asks for a tool that can do "offset
stripline", then I don't expect this person to know all the PCB processing
details yet, as I haven't seen any absolute symmetrical diff-trace in my
life. In reality they are all offset (sometimes a bit, sometimes a bit
more).
You are absolutely right, that no one should ever trust a free tool up to a
point where mistakes can cost money. But free tools can be supportive.
BR
Gert
PS: will you have a DC Booth again this year? If so, I'll stop by for a
talk.
----------------------------------------
Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.: HRB
8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm. Edgar-Peter Düning,
Dipl.-Ing. Torsten Ratzmann, Dr.-Ing. Alexander Rost
-----Ursprüngliche Nachricht-----
Von: Lee [mailto:leeritchey@xxxxxxxxxxxxx]
Gesendet: Donnerstag, 3. Januar 2013 18:38
An: Havermann, Gert; SI-List
Betreff: Re: [SI-LIST] AW: Asymmetric differential stripline impedance
Polar's CITS25 is an equation based tool that is accurate only part of the
time. It does not use a field solver. I don't trust its results.
As with most free tools, they are often worth the price!
-----Original Message-----
From: Havermann, Gert
Sent: Wednesday, January 02, 2013 11:54 PM
To: SI-List
Subject: [SI-LIST] AW: Asymmetric differential stripline impedance
Polar's CITS25 software is quite accurate and easy to use. It comes with
several different impedance cells. Even though Polar is no longer supporting
this tool, you will still be able to find the free evaluation version
somewhere in the web. The only evaluation restriction is the total number of
calculations, and it can be reset with uninstalling and re-installing.
BR
Gert
----------------------------------------
Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.: HRB
8808; Vertretungsberechtige Geschäftsführer: Dipl.-Kfm. Edgar-Peter Düning,
Dipl.-Ing. Torsten Ratzmann, Dr.-Ing. Alexander Rost
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Hithesh
Gesendet: Donnerstag, 3. Januar 2013 06:04
An: SI-List
Betreff: [SI-LIST] Asymmetric differential stripline impedance
Hi foks,
Is there any online tool to calculate the impedance of assymetric
differential stripline?
I searched, nothing available for asymmetric differential. It's either
asymmetric stripline or symmetric differential.
How to calculate differential impedance from single ended impedance?
This is with reference to USB signals.
Thanks
-Hithesh
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