[SI-LIST] Re: Speed Limit for dual stripline diff pairs?
- From: "Hassan O. Ali" <hassan@xxxxxxxx>
- To: "SI_LIST (E-mail)" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 3 Jul 2002 18:37:24 -0400 (EDT)
Patrick,
Your question is so difficult to answer because it begs so many other questions
that
need answers:
- what do you mean by "dual stripline config"? Dual stripline differential
pair? Two
orthogonal asymmetric striplines?
- which board substrate? FR4? N4000-13 SI?
- what do you mean by "speed"? Data rate? Velocity of wave propagation?
- which rise time?
- which data pattern? random? 8B/10B encoded?
- with or without pre-emphasis/equalization?
- what link type? chip-to-chip on a board? chip-to-chip across a backplane?
- which link performance parameters? eye mask? jitter?
- which link discontinuities? vias? packages? pads?
- etc?
In short, max. data-rate (if that's what you meant by speed) supported by a
certain PCB
trace configuration is a function of soooo many variables.
Regards.
Hassan.
On Jul 3 , "Patrick O'Shea" <patricko@xxxxxxxxxxxxxxxxx> wrote:
>
>
> Gents,
>
> What is the speed threshold for the use of a dual stripline config on a
> copper interconnect <12"? Can you achieve a higher speed with a microstrip,
> or dual stripline structure, or does it really matter?
>
> Patrick
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