[SI-LIST] Re: Spacing rules for reduction of cross talk
- From: "Kedar P. Apte" <kedar@xxxxxxxxxxxxxxxxx>
- To: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>, <nicklas@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 7 Jan 2005 10:22:17 +0530
Hello All,
thanks a lot to all who contributed in explaning me their experiences and
theory as well.
Thanks a lot again to Brian, Nicklas, Istvan, Vijay, John and every body. It
helped me a lot to improve my knowledge
Rgds
Kedar
----- Original Message -----
From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
To: <nicklas@xxxxxxxxx>; <kedar@xxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Thursday, January 06, 2005 10:54 PM
Subject: RE: [SI-LIST] Re: Spacing rules for reduction of cross talk
> Hi Kadar,
>
> X-talk is of course a very complex effect and so simulation is required
> to fully characterize it for a given PCB stackup and board route,
> however, there are some simplified concepts that can be useful when
> putting together initial geometry definitions. While trace width does
> impact x-talk, and the ratio of trace spacing to trace width (S/W) is
> one metric of x-talk control, it has been my experience that the more
> useful metric is trace spacing to dielectric height (S/H).
>
> A good coupling control strategy involves defining a board stackup with
> reasonable dielectric height that gives you a chance to adequately
> control x-talk with trace and space geometries that provide adequate
> routing density. I have found that a lot of mainstream PC designs for
> example use 4 mil cores with 4 mil traces to achieve 50-55 ohms nominal.
> This is pretty boring to most of the SIEs on this list, but it's useful
> for referecne. Once you have established this stackup and geometry then
> x-talk control can be implemented to the first order through controlling
> the trace spacing vs dielectric height ratio S/H. For example you might
> allow 1H (4 mil)spacing for breakout, then 2H (8 mil) spacing for busses
> where moderate coupling is allowed, with 3H or 4H spacing where your
> more sensitive to coupling, and even 5H on critical clocks and strobes.
> But this only gives you a first order estimate and you need to simulate.
>
>
> Because the stackup and geometry example I used had 4 mil trace width
> and 4 mil dielelctric height one can get similar results using the ratio
> of trace spacing to trace width (S/W), but this only works for the
> special case decsribed. The real metric of concern is S/H, but again
> this is only a first order metric.
>
>
> Brian P. Moran
> Senior SIE Engineer
> Intel Corporation
> brian.p.moran@xxxxxxxxx
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Nicklas
> Sent: Thursday, January 06, 2005 8:38 AM
> To: kedar@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Spacing rules for reduction of cross talk
>
> Hi Kedar,
>
> Adding to previous speakers on this topic, a good parametric plotting
> visual aid for the effects of varying the PCB height, trace width and
> trace pitch, and dielectric materials as a function of both impedance
> and crosstalk can be found at this link:
> http://www.interactive-products.com/IFSPro_Parms.htm
> The visual tool bar shows plot trends for each of these behaviors, and
> is a good visual intuition development aid.
>
> Following are a couple of examples or illustrations that can be found at
> the link, of impedance and cross talk interdependencies.
> - If you increase the conductor width, the impedance will decrease, and
> the cross talk increases.
> - If you increase the conductor pitch (conductor width + separation),
> the impedance increases and ultimately asymptotes (levels off) as the
> cross talk decreases as a result of the decoupling of the conductors.
> - If you decrease the dielectric height with regards to ground you
> decrease the impedance and decrease the crosstalk.
>
> Cheers.
>
> Nicklas
>
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