[SI-LIST] Source synchronous interface delay measurement
- From: "QU Perry" <Perry.Qu@xxxxxxxxxxxxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 15 Mar 2007 09:38:16 -0500
Hi,
I'm working on a DDR2 interface lately and come across some questions on
doing timing analysis and measure propagation delay in simulation. In
the traditional common clock scheme, what we learned is that we need to
measure prop delay for data/clock signals separately using standard IBIS
reference load with respect to actual receiver. So in simulation this is
done by:
1. connect output buffer to reference load and get a waveform;
2. connect output buffer to actual circuit and get the waveform at
receiver;
3. Measure delay between Vmeas at reference load and Vinl/Vinh at actual
receiver;
We need to this for both clock and data and get the prop delay for
timing analysis.
For source synchronous interface, since what we really care is the
relative skew between DQ and strobe, or between Addr and CLK/CLK# at
receiving device, and the fact that all output buffer for the same
interface share same reference load, I think what we should do is to
measure the difference in delay directly as below:
1. Simulate DQ signal and get receiver waveform;
2. Simulate DQS/DQS# and get receiver waveform;
3. Overlap the two and measure the difference between cross point of
DQS/DQS# and DQ Vinl/Vinh.
Unfortunately most SI tools I used do not support automatic measurement
for such scenario.
Another issue is related to prop delay measurement for CK/CK# when there
is a buffer involved, e.g., I have 5 loads on a DDR2 interface and there
is only one output at controller. When I place a zero-delay clock buffer
between controller and RAM, how do I measure the delay from controller
to RAM for clock ? I would think we need to sum up the delay from
controller to buffer, and then delay from buffer to RAM, also taking
into account any jitter/skew the clock buffer might introduce. The thing
that I tried to figure out is:
1. Controller - > buffer: what's the input reference voltage to use for
the buffer ?
2. Buffer to RAM: what's the output reference load I should use for
delay measurement ?
Can't really find much information on the clock buffer datasheet and
seems equally difficult to get anything from the vendor. Shouldn't this
be defined by the JEDEC standard as well ?
Thanks
Perry
=======================================
Perry Qu
Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu@xxxxxxxxxxxxxxxxxx
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