[SI-LIST] Re: Some reference on reference planes
- From: "N. Paul Taddonio" <paul.taddonio@xxxxxxxxxxxxxx>
- To: "Mark Grobman" <markgrobman@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 7 Nov 2011 16:22:26 -0500
You should at least provide decoupling capacitors from the signal's ref
plane to the
driver power plane and the driver gnd plane, located as close to the
driver's power pins as possible.
That way you can complete the return current path.
----- Original Message -----
From: "Mark Grobman" <markgrobman@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Monday, November 07, 2011 4:15 PM
Subject: [SI-LIST] Some reference on reference planes
> Hello experts,
> I require some help on the subject of reference planes. I'm designing a
> board and despite my best efforts i'm stuck with a situation where I'm
> forced to conduct a signal using a stripline neither of whose planes are
> the reference planes of the signal's driver (not the driver's ground or
> VCC).
>
> Now I know from various App. notes and books that this sort of situation
> should be avoided and that I have been a bad engineer indeed.
>
> Still, assuming the situation cannot be avoided I was hoping to get
> some quantitative approximation to how bad of an idea this is.Sadly
> speaking I don't have access to a 3d simulator which can give me exact
> results so I'm going for best effort design methods. I would love to get
> your input on the following issues:
>
> 1. Does the interference caused by not using the correct ref. planes carry
> throughout the transmission line or does it occur only at the edges where
> the current "jumps" back to the correct ref. planes?
> 2. Is there a merit figure of RiseTime/planes capacitance/???? for which
> the situation isn't problematic?
> 3. Will using diff. lines improve the situation?
> 4. Suggested reading on the matter.
> 5. Highly insightful remarks which will blow my mind.
>
> Cheers,
> Mark
>
>
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