One of the issues I see designers make when evaluating vias is understanding
the limitations of rules-of thumb. The biggest gotcha, even for experienced
designers, is what is happening with the ground current around the via. The
signal via tends to be pretty easy to understand. However, in order to maintain
transmission line characteristics through a via (the R, L, G, and C that make
up the z0, alpha, and beta of a line section), the ground part of the circuit
has to be preserved. This isn't always easy, there are usually several power
and ground planes in a circuit board that you are punching through with a via.
I have seen lots of cases where the planes around a via are so disjointed and
carved up that what should be a decent via doesn't work because the ground path
is awful. I've even seen waveguide modes between planes being excited, although
for most geometries this only happens above 25 Ghz or so. So, remember to
design the whole loop, not just the "signal half". You can make the most
perfect stub-free via in the world and still have difficulty with the ground.
Also, differential signaling isn't a free lunch for vias. It can help, but
often differential vias introduce mode conversion if there is skew in the
signal when it hits the via. In that case, the via needs to be designed for
good impedance matching in both the z0-diff case and the z0-common case. Mode
conversion, even if absorbed by good common mode termination in the driver and
receiver, is still a loss of signal power and a source of jitter.
Josiah Bartlett
Principal Engineer
Tektronix, Inc.
T 503.627.2946
http://tek.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Scott McMorrow
Sent: Wednesday, October 12, 2016 6:10 AM
To: antokdavis@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Solving signal integrity problems at very high data
rates - EDN
Key factor is length of the plated through hole. This is without stub, and
depends upon correct via design. Stubs dominate.
This does not mean that you will not see a lower impedance passing through a
via. Rather, the lengths of the discontinuities as a signal passes through a
via structure become distributed, because of the size vs.
wavelength of the signal. 12.5 GHz is the Nyquist frequency for a 25 Gbps
signal. With an 80 ps period, a 100 mil long via that is only 15 ps long is
seen to have all pad capacitance distributed across the structure.
All of this is just to say that "vias ain't the problem", in ultra high speed
signalling. At least not until we get to 50 and 100 Gbps.
Dielectric losses are also not the problem. But metal losses are. We need
more copper surface area to go faster, and we are not going to get that with
traces on dense printed circuit boards.
Scott McMorrow
Technical Director SI/PI
16 Stormy Brook Rd
Falmouth, ME 04105
(401) 284-1827 Business
http://www.teraspeed.com
On Wed, Oct 12, 2016 at 8:47 AM, Anto Kavungal Davis <antokdavis@xxxxxxxxx>
wrote:
Hi,
I was going through Solving signal integrity problems at very high
data rates - EDN, by Lee Ritchey, Scott McMorrow & Kella Knack
-October 04, 2016 Any papers/publications based on the following
comment or with similar results.
"What has been demonstrated by simulations as well as by laboratory
measurement is that when a signal travels the length of the plated
through hole or via, the parasitic capacitance of the hole is
distributed along the length of the hole, rendering it virtually invisible."
Thanks,
Anto
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