Lee,
The fix is of no practical significance for the speeds and bandwidths our
customers are interested in (>40GHz).
However, the 3D EM analysis comparison of localized VIA with Stub, Backdrilled
VIA, and this boomerang contraption is interesting from a 3D EM simulation
perspective. I am interested in adding to our next generation platform if I
can.
Intel also, to my knowledge, has a patent on a controlled impedance via, and
one on skew reduction based on pcb fabric weave.
- Al
Products for the Signal Integrity Practitioner
Alfred P. Neves
Chief Technologist
Office: 503-679-2429
www.wildrivertech.com <http://www.wildrivertech.com/>
2015 Best In Design&Test Finalist
On Dec 22, 2016, at 3:28 PM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx> wrote:
Al, right!
I have test traces with vias "hinging down" that show some pretty poor bad
passes at thie frequency.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Alfred P. Neves
Sent: Thursday, December 22, 2016 1:39 PM
To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
Cc: telegrapher9@xxxxxxxxx; Bayer <David.Bayer@xxxxxxxxxx>; si-list
<si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Solving signal integrity problems at very high data
rates - EDN
From what I see from the Intel presentations it shows improvements of
resonance at 8GHz with the benefit of not requiring the expensive backdrill.
The return loss does not improve, however.
Considering the data is limited is this correct Lee?
- Al
Products for the Signal Integrity Practitioner
Alfred P. Neves
Chief Technologist
Office: 503-679-2429
www.wildrivertech.com <http://www.wildrivertech.com/>
2015 Best In Design&Test Finalist
On Dec 22, 2016, at 9:25 AM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx> wrote:connector pin to which a trace on outer top connects from a BBA pin to a
Sure. A boomerang via is just an ordinary via drilled right next to the
connector pin. Instead of connecting directly to the connector pin the
connection is made to this via and then the connection from the via to the
connector pin is made on the bottom layer.
technique has been used for several years around the industry which
I am amazed, but not surprised, that a patent was issued for this. This
constitutes prior art. Patents are not valid that try to patent prior art.
On Behalf Of Dave Cuthbert
Hope this clears up the issue for you.
Lee
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
Sent: Tuesday, October 18, 2016 1:59 PMrates - EDN
To: Bayer <David.Bayer@xxxxxxxxxx>; si-list <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Solving signal integrity problems at very high data
<David.Bayer@xxxxxxxxxx> wrote:
Is this what is shown in US patent 7,501,586?
Dave CuthbertOn Oct 18, 2016 14:46, "Bayer, David (US COM)"
On Behalf Of Lee Ritchey
Could you elaborate on what a boomerang via is / how it is constructed?
Thanks
David
--
David Bayer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
data rates - EDNSent: Wednesday, October 12, 2016 11:37 AM
To: antokdavis@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Solving signal integrity problems at very high
Intel, you would find that they recommend a thing called a boomerang via to
If you attended the PCIe Gen 3 boot camp at DesignCon 2016 put on by
get from a trace on the top of a PCB to a through hole connector pin
without the need to remove the via stub. This is an example of distributing
the parasitic capacitance of the via barrel along its length, which is an
inductor, to minimize its effect on the signal.
transmission line just like the traces.
IF you think about it, what is being done is using the via as a
account for manufacturability issues, the vias, when traveled length wise,
When the dimensions of the vias under a 1 mm pitch BGA are done to
will be slightly higher in impedance that 50 ohms. This is fine as the
reflection from this, which will be quite small, is overshoot which does not
erode the signal noise margin.
has the switch cards on one side and the line cards on the other at right
Same thing happens when a large router is designed with a mid plane that
angles with all of the fast signals only in the plug in cards and none on
the backplane itself. All of the fast signals travel the length of the
plated through holes in the backplane.
boomerang vias.
Only on the plug in cards is it necessary to employ back drilling or
measurements.
Hope this clears this up a bit.
All of the above statements have been verified with many lab
On Behalf Of Anto Kavungal DavisProbably doesn't surprise those of you who know me.
Lee
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
ratesSent: Wednesday, October 12, 2016 5:47 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Solving signal integrity problems at very high data
rates - EDN, by Lee Ritchey, Scott McMorrow & Kella Knack -October 04, 2016- EDN
Hi,
I was going through Solving signal integrity problems at very high data
Any papers/publications based on the following comment or with similar
results.
measurement is that when a signal travels the length of the plated through
"What has been demonstrated by simulations as well as by laboratory
hole or via, the parasitic capacitance of the hole is distributed along the
length of the hole, rendering it virtually invisible."
------------------------------------------------------------------
Thanks,
Anto
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