Zicon and later, Sanmina had patents on buried capacitance they knew to be
invalid, but still threatened anyone who used buried capacitance in a
stackup unless they specified ZBC. Anyone remember that?
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Chuck Corley
Sent: Thursday, December 22, 2016 2:55 PM
To: telegrapher9@xxxxxxxxx
Cc: Bayer <David.Bayer@xxxxxxxxxx>; si-list <si-list@xxxxxxxxxxxxx>;
si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Solving signal integrity problems at very high data
rates - EDN
It appears to be an Intel patent application, so knowing them as a fairly
honest company hopefully they wouldn't show it in publications without
disclosing they have a patent on it, or allowing free use of it
??
Yes, I know that other companies have actually done this in the past (added
patented technologies to standards and later try to sue everyone who built
using standard, etc.), but I'm hoping Intel isn't like that.
Chuck Corley
On 2016-10-18 13:58, Dave Cuthbert wrote:
Is this what is shown in US patent 7,501,586?<David.Bayer@xxxxxxxxxx> wrote:
Dave CuthbertOn Oct 18, 2016 14:46, "Bayer, David (US COM)"
Intel, you would find that they recommend a thing called a boomerang via to
Could you elaborate on what a boomerang via is / how it is constructed?
Thanks
David
--
David Bayer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Lee Ritchey
Sent: Wednesday, October 12, 2016 11:37 AM
To: antokdavis@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Solving signal integrity problems at very high
data rates - EDN
If you attended the PCIe Gen 3 boot camp at DesignCon 2016 put on by
transmission line just like the traces.
IF you think about it, what is being done is using the via as a
account for manufacturability issues, the vias, when traveled length wise,
When the dimensions of the vias under a 1 mm pitch BGA are done to
has the switch cards on one side and the line cards on the other at right
Same thing happens when a large router is designed with a mid plane that
boomerang vias.
Only on the plug in cards is it necessary to employ back drilling or
measurements.
Hope this clears this up a bit.
All of the above statements have been verified with many lab
rates - EDN, by Lee Ritchey, Scott McMorrow & Kella Knack -October 04, 2016Probably doesn't surprise those of you who know me.
Lee
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Anto Kavungal ;
Davis
Sent: Wednesday, October 12, 2016 5:47 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Solving signal integrity problems at very high
data rates
- EDN
Hi,
I was going through Solving signal integrity problems at very high data
measurement is that when a signal travels the length of the plated through
"What has been demonstrated by simulations as well as by laboratory
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Thanks,
Anto
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