Could you elaborate on what a boomerang via is / how it is constructed?
Thanks
David
--
David Bayer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Lee Ritchey
Sent: Wednesday, October 12, 2016 11:37 AM
To: antokdavis@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Solving signal integrity problems at very high data
rates - EDN
If you attended the PCIe Gen 3 boot camp at DesignCon 2016 put on by Intel, you
would find that they recommend a thing called a boomerang via to get from a
trace on the top of a PCB to a through hole connector pin without the need to
remove the via stub. This is an example of distributing the parasitic
capacitance of the via barrel along its length, which is an inductor, to
minimize its effect on the signal.
IF you think about it, what is being done is using the via as a transmission
line just like the traces.
When the dimensions of the vias under a 1 mm pitch BGA are done to account for
manufacturability issues, the vias, when traveled length wise, will be slightly
higher in impedance that 50 ohms. This is fine as the reflection from this,
which will be quite small, is overshoot which does not erode the signal noise
margin.
Same thing happens when a large router is designed with a mid plane that has
the switch cards on one side and the line cards on the other at right angles
with all of the fast signals only in the plug in cards and none on the
backplane itself. All of the fast signals travel the length of the plated
through holes in the backplane.
Only on the plug in cards is it necessary to employ back drilling or boomerang
vias.
Hope this clears this up a bit.
All of the above statements have been verified with many lab measurements.
Probably doesn't surprise those of you who know me.
Lee
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Anto Kavungal Davis
Sent: Wednesday, October 12, 2016 5:47 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Solving signal integrity problems at very high data rates
- EDN
Hi,
I was going through Solving signal integrity problems at very high data rates -
EDN, by Lee Ritchey, Scott McMorrow & Kella Knack -October 04, 2016 Any
papers/publications based on the following comment or with similar results.
"What has been demonstrated by simulations as well as by laboratory measurement
is that when a signal travels the length of the plated through hole or via, the
parasitic capacitance of the hole is distributed along the length of the hole,
rendering it virtually invisible."
Thanks,
Anto
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