[SI-LIST] Si-simulation Methodology
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 30 Mar 2010 20:23:21 +0100
Hello,
I would like to ask you guys about Si-simulation Methodology. If an already
designed board layout is given, what signal combinations do you simulate as
a verification before ordering the board for manufacturing?
How to quantify the results?
What is the Pass/Fail condition?
What is the simulation setup/stimulus? (Some programs dont give much
choices, but others do)
What should be the methodology or signal-integrity-checklist for a digital
board?
I think these simulations would make sense:
(what else would you recommend?)
1. time domain:
-Parallel Buses, maximum overshoot/undershoot amplitude, check if that
violates the electrical abs/max rating specs or the transmitter/receiver
chips or not.
-Parallel Buses, min/max signal propagation delay (flight time together with
transition time and ringing) with ISI/noises, check intermediate timing
margins (relative timing to strobe/clock) or propagation delays (absolute
timing from simulation time zero). Use the results for timing analysis
calculations.
-Parallel Buses, crosstalk WITHIN one signal group. One signal group is a
group of signals that are clocked out on the same clock edge. For example a
DDR-SDRAM memory databus lane, or a memory address/comman bus, or a whole
PCI bus. For the simulation, the victim is held low, the aggressor is
switching, see the amplitude of the FEXT? WHAT DOES THIS TELL US? This will
not cause false detection, since the signals in a group switch in the same
time, and it does not happen when they are being sampled.
-Parallel Buses, crosstalk WITHIN one signal group. The victim is rising,
the aggressor is falling (and the opposite combination as well), they are at
maximum worst-case skew specified on the datasheets, check the setup/hold
margin decrese from the no-aggressor case. Use this information for timing
analysis calculations.
-Parallel Buses, crosstalk BETWEEN different signal groups. The victim is
held low, the aggressor is switching, see the amplitude of the FEXT and
NEXT. If it is enough to make the victim to cross the logic thresholds or
not. If this happens when the signal is sampled, then it causes false
detection.
-Parallel Buses, crosstalk BETWEEN different signal groups. The victim is
rising, the aggressor is falling (and the opposite as well), they are at
t_rise delayed to each other, see the setup/hold margin decrese from the
no-aggressor case. Use this information for timing analysis calculations.
-Parallel Buses, crosstalk FROM a power plane. The victim is held low, the
the power rail is bouncing , see the amplitude on the signal net. If it is
enough to make the victim to cross the logic thresholds or not. If this
happens when the signal is sampled, then it causes false detection. The
setup could be: pulse source in series with the IBIS buffer supply rail
(effect on the RX or TX buffer), or generate a plane+signal touchstone
macromodel (effect on the PCB trace) in an EM simulator.
-Parallel Buses, crosstalk FROM a power plane. The victim is switching, the
the power rail is bouncing , they are at t_rise or max-skew delayed to each
other, see the setup/hold margin decrese from a no-aggressor simulation
result. Use this information for timing analysis calculations. The setup
could be: pulse source in series with the IBIS buffer supply rail (effect on
the RX or TX buffer), or generate a plane+signal touchstone macromodel
(effect on the PCB trace) in an EM simulator.
-Use a powerplane touchstone model + decoupling model with multiple IBIS
drivers driving ideal transmission lines. Check the noise generated. Use
that voltage value in a plane-to-signal crosstalk simulation.
-Use a powerplane+trace touchstone model + decoupling model with multiple
IBIS drivers driving the real PCB traces included in the same touchstone
model. Check the noise generated. Use that voltage value in a
plane-to-signal crosstalk simulation.
-Power/Gnd plane pair resonances. Maximum noise amplitude when excited by
IBIS buffer models.
-High Seed serial: eye diagram simulation, with/without equalizer modeling
and with/without pre/de-emphasis. Bathtub curve to check target-BER eye
width. Jitter histogram to find the source of problems.
-Crosstalk from signals and power rails to clocks: Measure clock jitter and
check monotonity.
-What else?
2. Frequency domain:
-Interconnect EM simulation to get s-parameter model, to check: insertion
loss (for loss budget calculation), resonances, mixed mode S-parameters for
mode transformation and differential attenuation.
-Interconnect EM simulation to get s-parameter model, to check: crosstalk
over frequency. Compare crosstalk of different PCB trace structures or
stackups at a chosen (signalling) frequency.
-Power plane + decoupling for impedance versus Z-target, and for checking
resonance frequecies. Do a simple time domain simulation where the IBIS
buffer power supply is a voltage source with a series resistor at the value
of the peak plane impedance.
-What else?
Best regards,
Istvan Nagy
Hardware Design Engineer
Concurrent Technologies
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