[SI-LIST] Re: Single ended Noise OR Differential Noise

  • From: Sanjeev Gupta <skgupta.sanjeev@xxxxxxxxx>
  • To: Scott McMorrow <scott@xxxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
  • Date: Thu, 9 Oct 2014 22:19:20 +0530

Thanks Scott for your idea.
We will experiment on this and keep updated....
Thanks
Sanjeev

On Thu, Oct 9, 2014 at 5:29 PM, Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:

> Sanjeev
>
> Yes, this is quite possible to reference to a "universal ground". You just
> have to create a new pec plane in the design that is removed from the
> surrounding structures so that it does not couple, and reference ports to
> this plane.  At it's corners it can be strapped with large resistors to
> provide isolation and a DC connection.  You then have to insure that there
> is a very large boundary, so that stray fields remain in the design, and
> use a high resolution solution to reduce noise in the full wave solution.
>
> It's a pain, but is quite possible.
>
> regards,
>
> Scott
>
>
> Scott McMorrow
> Teraspeed® Consulting - A Division of Samtec
> 16 Stormy Brook Rd
> Falmouth, ME 04105
> (401) 284-1827 Business
> http://www.teraspeed.com
>
> On Thu, Oct 9, 2014 at 1:21 AM, Sanjeev Gupta <skgupta.sanjeev@xxxxxxxxx>
> wrote:
>
>> is it possible to extract Vss and Vcc s-parameter respect to ideal
>> reference?  I doubt, any tool can do this kind of  s-parameter extraction.
>> if such s-parameter extraction is not possible. do you suggest to use RLC
>> models of VCC and VSS based on quasi-static extraction (using Q3D) for SSN
>> problem solution.
>>
>> Thanks
>>
>>
>> On Wed, Oct 8, 2014 at 9:47 PM, Iliya Zamek <dmarc-noreply@xxxxxxxxxxxxx>
>> wrote:
>>
>> > Hi Naresh,
>> > Steve described in details many reasons why receiver might see a noise
>> > when you applied in-phase noise to Vss and Vcc. It is also important to
>> > know some more details about your experiments to make a conclusion.
>> Whether
>> > you were using oscilloscope, or receiver to measure output jitter and
>> > noise, and how you applied noise to Vss and Vcc. In addition to Steve
>> > observation, different "modulation sensitivity" of Vss and Vcc,  the
>> > pre-driver to the jitter contribution, and just simple conversion of
>> > waveform' shift to the jitter, - all might contribute to the output
>> jitter
>> > and noise. I agree with you that I/O delay respect to the Vss
>> "disturbance"
>> > also one of the reason of remaining noise.
>> > I also agree with you that it is good to extract both Vss and Vcc
>> respect
>> > to ideal reference, which is not so easy to simulate. However, if you
>> can,
>> > there is even more important reason to do so. If you have other signals
>> > switching along with you measured, these others will contribute through
>> > common Vss to the Vss noise. So, all depends on details how you applied
>> > noise and did measurements.
>> > Thank you.Iliya
>> >      On Tuesday, October 7, 2014 11:50 PM, Naresh Dhamija <
>> > naresh.dhamija@xxxxxxxxxxxxx> wrote:
>> >
>> >
>> >  Hi Iliya,
>> >
>> >
>> > I understand that different blocks inside IO will convert the in phase
>> > noise to differential noise and will cause jitter within the IO, but at
>> the
>> > output of IO pad w.r.t noise vss, I see some noise, I guess it is
>> because
>> > of finite delay within the output stage of IO . Is this correct?
>> >
>> >
>> >
>> > If it is so, then my follow up question is:
>> >
>> > In the complete system simulation, when we plug package and board
>> > s-parameter models, it is good to have both vddio and vss extracted
>> w.r.t
>> > ideal ground rather than only vddio extracted which will only have
>> > differential noise of vddio with its local vss where common noise of
>> vddio
>> > and vss is missed out.
>> >
>> >
>> >
>> > Regards
>> >
>> > Naresh
>> >
>> >
>> >
>> > *From:* Iliya Zamek [mailto:i_zamek@xxxxxxxxx]
>> > *Sent:* Wednesday, October 08, 2014 12:38 AM
>> > *To:* naresh.dhamija@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>> > *Subject:* Re: [SI-LIST] Single ended Noise OR Differential Noise
>> >
>> >
>> >
>> > Hi Naresh,
>> >
>> >
>> >
>> > Your observation is correct. The impact of PDN noise on on-chip signals
>> > timing and logic levels noise is different. The impact on I/O Jitter is
>> > more complex.
>> >
>> > The impact on logic levels' noise does not depend on noise frequency and
>> > I/O signal frequency interrelationship, but impact on I/O' Jitter does.
>> You
>> > might want to see the results of research of impact noise on Jitter in a
>> > paper (and references) by Google: "On-chip Jitter and system Power
>> > Integrity", I. Zamek, Designcon 2012
>> >
>> >
>> >
>> > Also, there are two effects to consider at I/O Jitter analysis: impact
>> on
>> > Pre-Driver and impact on output Buffer. Impact on Pre-Driver contribute
>> > mainly on Jitter, the impact on Buffer contributes on both, Jitter and
>> > Logic levels' noise. You might see the research and experiments on I/O
>> > jitter in reference #16:
>> >
>> > Zhe Li, Iliya Zamek, Peter Boyle, ―FPGA IO Timing Variations with SSO
>> > Noise,‖ DesignCon 2008
>> >
>> >
>> >
>> > Thank you.
>> >
>> >
>> >
>> > Iliya Zamek
>> >
>> >
>> >
>> >
>> >
>> > On Tuesday, October 7, 2014 6:10 AM, Naresh Dhamija <
>> > naresh.dhamija@xxxxxxxxxxxxx> wrote:
>> >
>> >
>> >
>> > Hi folks,
>> >
>> > I am doing power noise analysis on a system that uses SSTL IO buffers. I
>> > am seeing the ripple on the IO output signal - such that during hi state
>> > IO output signal follows the noise whatever is on the vddio and during
>> low
>> > state, IO output signal follows the noise on the vss. Observing this
>> > phenomenon, I purposely forced IN PHASE single ended noise  to both
>> vdddio
>> > and vss of almost the same frequency as of data rate but uncorrelated
>> with
>> > data rate. Since noise forced to vddio and vss are IN PHASE so
>> > Differential Noise measured between vddio and vss at each instant shows
>> > zero noise. But still I see jitter on the edges because of finite rise
>> and
>> > fall times, the initial low level and final high level for a transition
>> > from low to hi are not always same. Does this mean that along with
>> > differential noise, single ended noise on power and ground also cause
>> > jitter to IO driver.
>> >
>> > Regards
>> > Naresh
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>>
>> --
>> Thanks
>> Sanjeev
>>
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>


-- 
Thanks
Sanjeev

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