[SI-LIST] Re: Single ended Noise OR Differential Noise

  • From: "Iliya Zamek" <dmarc-noreply@xxxxxxxxxxxxx> (Redacted sender "i_zamek@xxxxxxxxx" for DMARC)
  • To: "naresh.dhamija@xxxxxxxxxxxxx" <naresh.dhamija@xxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 7 Oct 2014 12:08:03 -0700

Hi Naresh, 
Your observation is correct. The impact of PDN noise on on-chip signals timing 
and logic levels noise is different. The impact on I/O Jitter is more complex.
The impact on logic levels' noise does not depend on noise frequency and I/O 
signal frequency interrelationship, but impact on I/O' Jitter does. You might 
want to see the results of research of impact noise on Jitter in a paper (and 
references) by Google: "On-chip Jitter and system Power Integrity", I. Zamek, 
Designcon 2012

Also, there are two effects to consider at I/O Jitter analysis: impact on 
Pre-Driver and impact on output Buffer. Impact on Pre-Driver contribute mainly 
on Jitter, the impact on Buffer contributes on both, Jitter and Logic levels' 
noise. You might see the research and experiments on I/O jitter in reference 
#16: 
Zhe Li, Iliya Zamek, Peter Boyle, ―FPGA IO Timing Variations with SSO 
Noise,‖ DesignCon 2008 


Thank you.

Iliya Zamek

 
On Tuesday, October 7, 2014 6:10 AM, Naresh Dhamija 
<naresh.dhamija@xxxxxxxxxxxxx> wrote:
 


Hi folks,

I am doing power noise analysis on a system
 that uses SSTL IO buffers. I
am seeing the ripple on the IO output signal - such that during hi state
IO output signal follows the noise whatever is on the vddio and during low
state, IO output signal follows the noise on the vss. Observing this
phenomenon, I purposely forced IN PHASE single ended noise  to both vdddio
and vss of almost the same frequency as of data rate
 but uncorrelated with
data rate. Since noise forced to vddio and vss are IN PHASE so
Differential Noise measured between vddio and vss at each instant shows
zero noise. But still I see jitter on the edges because of finite rise and
fall times, the initial low level and final high level for a transition
from low to hi are not always same. Does this mean that along with
differential noise, single ended noise on power and ground also cause
jitter to IO driver.

Regards
Naresh
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