[SI-LIST] Simulation using Common-mode Choke
- From: Ravinder.Ajmani@xxxxxxxx
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 22 Feb 2013 17:52:23 -0800
Content-Type: text/plain; charset="US-ASCII"
Hi Experts,
I am running simulation on 6 Gbps interconnects to study the effect of
common-mode chokes. I have S-parameter models for the common-mode chokes
obtained from the vendor. The Differential Insertion Loss for these
chokes is about 1.75 dB and 3 dB at 6 GHz, and Single-ended Insertion Loss
is about 10 dB to 12 dB. I am using Cadence PCB-SI simulator. The
Channel Simulation doesn't run because the Impulse waveform is all messed
up. If I perform regular time-domain simulation then the eye is
practically closed. Without the chokes the eye height is 800 mV.
Is it possible that the high common-mode loss is affecting the simulation
results. Is there another way to verify these components.
Thanks for the help.
Regards
Ravinder Ajmani
HGST, a Western Digital company
ravinder.ajmani@xxxxxxxx
5601 Great Oaks Pkwy.
San Jose, CA 95119-1003
www.hgst.com
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