[SI-LIST] Re: Simulation problems with SSTL2 IBIS model
- From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 19 Sep 2002 14:39:07 -0400
It might be interesting to run a simulation with just the output device
connected to the test load (L/C/R_fixture) specified in the
[rising/falling waveform] sections of the IBIS model, and compare them
with the actual V-T data in the model. They should be identical.
Do IBIS models contain enough information to correctly predict the
results from both rising and falling edges with respect to one another?
Since there's no timing reference for an output waveform, could the
rising and falling outputs just be skewed with respect to one another,
causing them to cross one another in the wrong place? (Maybe I'm just
not thinking clearly enough ... I am not a big fan of IBIS models when
transistor models exist; can't you tell?)
Andy
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