Hi SI-List members, I have performed some simulations using an IBIS model of a differential clock buffer and I wonder about the strange waveform behavior. The simulations have been computed with two very common simulation tools. The output signals cross near the low voltage state instead of in the middle of the high and low state. Furthermore high ringing occurs although the transmission lines are terminated properly. After some investigations of the IBIS file I found out, that the simulation results look much better, if the [ramp] data will be used instead using the [rising/falling waveforms]. But, of course these simulation results based on the ramp data don't correlate very well to the reference waveforms, which are based on an Hspice transistor level model. Therefore I tried to get some more simulation results which have been computed with some other tools. I was really surprised, that the new results of the other tools look quite well. From my point of view it seems, that the IBIS file is OK and that there might be some problems in our tools to handle this kind of IBIS file. So, I would like to know if someone of you had similar problems or an idea how to solve this problems. Thanks Dirk Linnenbruegger ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu