[SI-LIST] Simulation problems with SSTL2 IBIS model

  • From: Linnenbruegger Dirk <Dirk.Linnenbruegger@xxxxxxxxxxxxxxxxxxx>
  • To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 19 Sep 2002 13:37:03 +0200


Hi SI-List members,

I have performed some simulations using an IBIS 
model of a differential clock buffer and I wonder 
about the strange waveform behavior. 
The simulations have been computed with two very 
common simulation tools.

The output signals cross near the low voltage state 
instead of in the middle of the high and low state.
Furthermore high ringing occurs although the 
transmission lines are terminated properly.

After some investigations of the IBIS file I found 
out, that the simulation results look much better, 
if the [ramp] data will be used instead using the 
[rising/falling waveforms].

But, of course these simulation results based on the 
ramp data don't correlate very well to the reference 
waveforms, which are based on an Hspice transistor 
level model. Therefore I tried to get some more 
simulation results which have been computed with some 
other tools. I was really surprised, that the new 
results of the other tools look quite well.

From my point of view it seems, that the IBIS file is 
OK and that there might be some problems in our tools 
to handle this kind of IBIS file.

So, I would like to know if someone of you had similar 
problems or an idea how to solve this problems.


Thanks
Dirk Linnenbruegger  
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