[SI-LIST] Re: Signals crossing power plane splits
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 14 Nov 2013 09:06:53 -0800
Beware those "low frequency" signals because:
1. It's the edge rates that matter most.
2. I2C in particular is a very high impedance signaling standard that is
easily corrupted.
The road to hell is paved with "low frequency" signal SI violations.
The bypass capacitors form a common impedance for everything in the
cavity that acts in parallel to the impedance of the cavity proper.
Over the frequency range that they can be effective they reduce the
common impedance and therefore the cross-talk. What that frequency
range is depends on the capacitors and how far away they are from the
cavity and how they are attached to the cavity what the cavity thickness
is and what the dK of the material in the cavity is.
See for example:
http://www.ipblox.com/pubs/SVCEMC_Feb_2012/How%20Bad%20is%20Bad.pdf
Steve
On 11/14/2013 8:42 AM, Balaji G wrote:
> Hi all,
> We might have discussed about this subject here, but, I would like to get
> more perspective on this. We have some low frequency signals (I2C, JTAG)
> and some signals with rise time of 0.5ns routed in stripline between power
> splits and ground plane in which ground plane is close to the signal layer
> and power split far from signal layer facilitating 1:4 coupling. In this
> condition to provide connection between two power splits we generally
> stitch capacitors to provide AC return path in the power planes.
>
> My understanding is when we stitch only few capacitor for providing AC
> return path for many signals (say 8 to 10) their returns will couple when
> flowing through capacitors and leads to Xtalk noise. Even if we have more
> capacitors, the inductance will increase when returns flow through the via,
> to capacitor, again via then power power plane leading to impedance
> discontinuity.
>
> If I am right, when stitching capacitors equals to number of signals
> crossing splits, then having stitching capacitor is only intended for slow
> rising signals where the impedance discontinuity not significant and fast
> rising (0.5ns) MUST kept between solid planes? Is my understanding right?
>
> Regards,
> Balaji
>
>
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Steve Weir
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