[SI-LIST] Signal Integrity position at Juniper Networks
- From: "Luong Hoang" <luongh@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 6 Aug 2008 15:32:48 -0700
Hi all we're looking to fill some signal integrity positions at Juniper
Networks (Sunnyvale, CA).
If you're interested, you can contact the recruiter through his email at
BenW@xxxxxxxxxxx / BenW[at]Juniper.net
Here is a brief description...
System level signal integrity and timing analysis on boards, packages,
ASICs and FPGAs.
- Design timing (setup/hold board timing analysis and clock design).
- Simulate and measure board level reflection, xtalk, ground bounce,
power/ground noise.
- Perform simulations for on-chip SI including core noise modeling, on
chip crosstalk, I/O selection, chip pinout assignment, package selection
and pinout assignment.
- PWB cross-section design/tradeoff, serdes channel analysis.
- Use lab equipment such as oscilloscopes, Time Domain Reflectometers,
Vector Network Analyzers, Spectrum Analyzers. Good lab debug skills.
- Proficient with HSPICE, Allegro, SiSoft, Speed2K, PowerSI, Ansoft
HFSS.
- Good oral and written communication skills. Team player, willing to
take on a variety of projects, good listening skills, self motivator.
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