[SI-LIST] Signal Integrity Engineer-Bay area 8-18
- From: "Vijay Tailor" <vtailor1@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 19 Aug 2003 13:37:12 -0400
HOT Permanent Position for Signal Integrity Engineer for Public Company in the
Bay area
Vijay Tailor
1-888-743-4206
vtailor1@xxxxxxxxxxx
CHIP LEVEL SIGNAL INTEGRITY ENGINEER
Define, specify, test, and debug high speed single-ended and differential I/O
for a given bandwidth requirement (predriver, on-chip decoupling, termination,
physical design rules, etc.). Develop on-chip power and noise management
techniques. Thorough clocking and timing analysis of I/O interface. Work with
PLL/DLL/PDB (programmable delay block) design/implementation, SerDes, XAUI
interfaces
Must have transistor level circuit design background and knowledge of standard
interfaces (HSTL, SSTL, LVDS, CML). Must know common high speed I/O design
techniques (deskew, equalization, PVT compensation). Knowledge of semiconductor
processes and ASIC technologies. Must have lab experience and knowledge of how
to run HSPICE, Spectre. Able to work independently. Good communication skills
for working with vendors and design teams
Requires MSEE/CS combined with 5-7 years of related experience, or BSEE/CS
combined with 7-10+ yrs related experience.
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