[SI-LIST] Signal Integrity Engineer - Juniper Networks - Sunnyvale, CA
- From: "Ralph Kettler" <rkettler@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 30 Jun 2008 14:21:28 -0700
SIGNAL INTEGRITY ENGINEER - Juniper Networks - Sunnyvale, CA
Job Description:
System level signal integrity and timing analysis on boards, packages,
ASICs and FPGAs.
Design timing and clock distribution (setup/hold board timing analysis
and clock design).
Simulate and measure board level reflection, crosstalk, ground bounce,
power/ground noise.
Perform simulations for on-chip SI including core noise modeling, on
chip crosstalk, I/O selection, chip pin-out assignment, package
selection and pin-out assignment.
PWB cross-section design/tradeoff, serdes channel analysis.
Use lab equipment such as oscilloscopes, Time Domain Reflectometers,
Vector Network Analyzers, Spectrum Analyzers. Good lab debug skills.
Proficient with HSPICE, Allegro, SiSoft, Speed2K, PowerSI, Matlab,
Ansoft HFSS.
Good oral and written communication skills. Team player who is willing
to take on a variety of projects, good listening skills, self motivator.
For an immediate response, please send your resume to:
juniper@xxxxxxxx
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