[SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design

  • From: "hreidmarkailen" <hreidmarkailen@xxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Sat, 9 Sep 2006 12:26:58 -0400

correction, should be:
"...the 405mV really has to do with the 8.1mA min. drive spec in Table4."

 

(ClassII 405mV delta is only coincidence I think)

 

 

 

-----Original Message-----
From: hreidmarkailen [mailto:hreidmarkailen@xxxxxxxxxxx] 
Sent: Saturday, September 09, 2006 12:22 PM
To: 'si-list@xxxxxxxxxxxxx'
Subject: RE: [SI-LIST] Re: Setup-Hold Equations for Source Synchronous
Design

 

John,

 

Yes, your link is a 1998 version.  I have one from May 2002: JESD8-9B.  Go
to jedec.org and noodle around to the "free download" area. 

 

Apparently, the 405mV really has to do with the 8.1mA drive spec in Table4
for ClassII.  Looks like the bad flow of the document is the result of
editing incompletely:  that sentence should cite Table4.  The language in
the spec isn't very good wrt flowing along logically or making the best
reading.   8.1mA x 50ohm(Rtt) = .405V. at input. The assumption is that min.
drive is 8.1mA.  All results at Vin flow from that and Vtt wc assumptions.
Looks like Rtt is assumed to have tol. = 0%.  Also see Note2 in Table 4. 

 

"spla yer krunge"  party on 

 

 

 

-----Original Message-----

From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Hill, John

Sent: Thursday, August 31, 2006 4:08 PM

To: Cclewell@xxxxxxxxxxxxx; nrpatel@xxxxxxxxxxx

Cc: si-list@xxxxxxxxxxxxx

Subject: [SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design

 

Hello all,

 

I am reading page 149 of this book right now and am a bit confused. It

is describing SSTL_2 and declares that Vin must reach 405 mV above Vref.

Can someone tell me how you get the number 405?

 

BTW, the book identifies Vih(ac) and Vil(ac) at 0.31, but the

specification has 0.35. Is this an old specification?

 

http://download.micron.com/pdf/misc/sstl_2spec.pdf#search=3D%22sstl_2%22

 

Best regards,

 

John

 

 

 

=20

 

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-----Original Message-----

 

From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]

On Behalf Of Clewell, Craig

Sent: Monday, August 14, 2006 3:31 PM

To: 'nrpatel@xxxxxxxxxxx'

Cc: si-list@xxxxxxxxxxxxx

Subject: [SI-LIST] Re: Setup-Hold Equations for Source Synchronous

Design

 

Try Digital Techniques for High-Speed Design ~ Tom Granberg

ISBN#0-13-142291-X

 

-----Original Message-----

From: nrpatel@xxxxxxxxxxx [mailto:nrpatel@xxxxxxxxxxx]

Sent: Monday, August 14, 2006 3:14 PM

To: si-list@xxxxxxxxxxxxx

Subject: [SI-LIST] Setup-Hold Equations for Source Synchronous Design

 

 

Hello all,

Can someone point me out to a good reference that explains the setup and

 

hold margin calculations for a source synchronous design like DDR?

Did not have much luck googling.

 

Thanks,

Nikhil=20

 

 

 

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