[SI-LIST] Session of interest to SI engineers at DesignCon 2006
- From: "Pratt, Gary" <gary_pratt@xxxxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 2 Feb 2006 18:12:30 -0500
Please be advised of an update to the SI sessions at DesignCon next
week. In addition to the AMS tutorial you may have read about in the
last notice, there will be an interesting paper on SSN simulation with
large s-parameter models and IBIS 4.1; as well as a very interesting
application of AMS in a fully functional SI simulation of a DDR memory
interface. Please see the abstracts below, and if you are able to
attend any of these, please give me the opportunity to greet you
personally. =20
These 100% technical sessions will be of interest to high-speed device
suppliers, users, and SI tool vendors. These are a great way to become
familiar with the exciting capabilities of these new industry standards.
DesignCon 2006
Monday, February 6, 9:00 am - noon
Santa Clara Convention Center
http://www.designcon.com/2006/
TF-MA2: Introduction to IBIS 4.1 AMS SERDES Driver Modeling, and Other
Novel Applications of AMS Modeling=20
Modeling SERDES drivers has proven to be a significant challenge with
traditional modeling techniques. Fortunately, the IBIS committee
recognized this problem and ratified a new approach which offers
significant advantages over existing techniques. This tutorial will
enable the participant to understand and perhaps begin coding their own
IBIS 4.1 models. This skill will be exercised by going through a number
of actual examples of the standard and novel applications of its new
capabilities (such as DFE). This presentation will show how IBIS 4.1/AMS
is like having your own simulator programmer on staff. The applications
are only limited by the imagination.=20
DesignCon 2006
Wednesday, February 8, 9:40 am - 10:20 am
Santa Clara Convention Center
http://www.designcon.com/2006/=20
5-WA2: Fast Time-Domain Simulation of 200+ Port S-Parameter Package
Models
S-Parameters are quickly becoming the standard method in PCB SI analysis
to describe packages, channels, and connectors. This paper will
describe techniques for significantly improving the generation and
transient simulation of typical s-parameter models and large (200+ port)
s-parameter package models used for power distribution and simultaneous
switching noise analysis. We show that direct representation of
s-parameters by poles/residues is more efficient than creating
equivalent circuits or performing direct convolution.
This joint Altera/Mentor paper will also describe why it is important to
simulate channels in transient analysis, the caveats of alternate
frequency-domain channel analysis techniques, and how AMS models and
these new transient s-parameter simulation techniques makes it feasible
to perform transient simulation of hundreds of thousands of data
cycles.
DesignCon 2006 IBIS Summit Meeting
Thursday, February 9
Hyatt Regency Hotel, Magnolia Room
HDL and IBIS 4.1 Models in a Functional DDR Memory Interface Analysis
9:00 AM to 9:30 AM
The Multi-Lingual AMS extensions of IBIS 4.1 provide significant new
capabilities that can be used to implement many novel enhancements to SI
verification techniques and applications. This joint Micron/Mentor paper
will describe one such application that combines HDL functional models
and IBIS I/O models to perform a thorough Signal Integrity verification
of a complete Chipset to Memory interface. Electrical compliance and
timing are verified on all address, data (both directions), and control
lines in one simulation.
The IBIS meeting is from 8:00 to 5:00 and will feature many other
interesting presentations and discussions.
I hope to have the opportunity to meet you at one of these events.
Regards,
Gary Pratt
Gary L. Pratt, P.E.
Product Manager - High-Speed Design Kits SDD Division
Office: (503) 685-1177
Mobile: dial '0' at Voicemail, or
mobile: (262) 337-2196
Email: gary_pratt@xxxxxxxxxx
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