[SI-LIST] Re: Serpentine Traces

  • From: "Dunbar, Tony" <tony_dunbar@xxxxxxxxxxx>
  • To: 'SI-List' <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 10 Oct 2002 20:58:39 -0500

Jack,

I'm pleased to hear that! The timestep was precisely the kind of
"user-control issue" I was alluding to in my posting. Unless a sufficiently
small timestep is used, short, individual segments of routing can get lumped
with other adjacent segments and the true (electrical) length of the line is
not modeled. It is typically one of those accuracy vs. speed trade-offs.
Added to that, curved trace segments will not be represented accurately by
many 'trace modelers'.

Also, I completely agree that a unified method should be used to turn those
corners! It was another curiosity of your posting as to how you had ended up
with a mix of arcs and 45s.

Regards,
Tony

-----Original Message-----
From: Jack W.C. Lin [mailto:JackWCLin@xxxxxxxxxxxx]
Sent: Thursday, October 10, 2002 7:54 PM
To: Dunbar, Tony; 'SI-List'
Subject: RE: [SI-LIST] Re: Serpentine Traces


Hi Tony:
My problem had been solved due to the resolution of my SIM tool. If I set
more tiny time step for calculation, DQ and DQS will not differ too much. As
I depicted in the last mail, it did improve when I changed 45 degree bending
into arc bending for serpentine. Anyway, I suggest that unify routing
behavior (45 degree or arc bending for serpentine) is important for same bus
group routing especially for future DDR400 0r DDRII. More high speed signal
will resolve these tiny differences, that may induce extra uncertainty delay
issues.
Jack

-----Original Message-----
From: Dunbar, Tony [mailto:tony_dunbar@xxxxxxxxxxx] 
Sent: Thursday, October 10, 2002 1:56 AM
To: 'SI-List'
Subject: [SI-LIST] Re: Serpentine Traces



Jack,

I noticed that you had chosen to replace the 45s with the arc and not the
other way around (i.e. replace the arcs with 45s). The reason why I'm
curious about this is because I don't know how the algorithm commonly known
as the 'Trace Modeler' represents (breaks down) an arc. For that matter,
even handling short 45 degree or short orthogonal sections accurately may be
a user-control issue. I'm talking in general terms here, not XTK specific,
but I think 45s should be handled more consistently than arcs. I saw
somewhere that you had done a straightening out exercise, but I'm interested
to see what replacing the arcs with 45s yields - unless you told us and I
missed it.

Regards,
Tony

-----Original Message-----
From: Jack W.C. Lin [mailto:JackWCLin@xxxxxxxxxxxx]
Sent: Tuesday, October 08, 2002 7:46 PM
To: Robert Haller; ericg@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Serpentine Traces


Dear all:
As you know that serpentine routing will take shorter time to propagate
signal from source to load than a straight line. But I found an interesting
result from my case. In my DDR design,said some certain group. DQ length is
almost the same with DQS,DQ did a serious serpentine routing but DQS a
little. In our common sense,the flight time between them will differ a
little. But I found that they differ too much,around 1.4 ns. DQS leading DQ?
An unbelevable result. I found that DQ take 45 degree bending for
serpentine, and DQS take ARC serpentine. If I modified all serpentine of DQ
as ARC serpentine with same length, the flight time difference with DQS
reduce to around 0.8ns. It's improved but not good enough. (my case is
DDR333,flight_max=0.45ns,SIM tool is XTK). Is there any one experienced the
similiar case? Any suggestion is highly appreciated.
PS: I had delete all net but leave this problem DQ and related DQS, no other
extra coupling but themself due to serpentine routing. Jack Jack W.C. Lin
CAD&EMC Team in aopen In. 

------i(c)l?T(r)?-----
    ?HYoaI: "Robert Haller" <rhaller@xxxxxxxxxx>
    ?HYo$e?A:  2002/9/11 $W$E 02:19:22
    |?YoaI: "ericg@xxxxxxxxxxx" <ericg@xxxxxxxxxxx>
    1/2AEY>: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
    YD|(r): [SI-LIST] Re: Serpentine Traces
    
    
    Eric ,
        For the example given, 176 ps/in -> 170 ps/in the difference was 
    between 5/50 and 5/20 (Line width, /Line Spacing). The delay variations 
    were even more dramatic at tighter spacings.
    
    To answer Andy's question, I click Info in Allegro - which I believe 
    measures the center of the line.
    
    Regards,
    Bob
    -- 
    Robert J. Haller (rhaller@xxxxxxxxxx)
    Principal Consultant
    Signal Integrity Software Inc.
    6 Clock Tower Place, Suite 250
    Maynard, MA 01754
    Phone: (978) 461-0449, ext 15
    
    
    Eric Goodill wrote:
    > Bob,
    > 
    > What is 'close' in your test board?
    > 
    > -Eric
    > 
    > Robert Haller wrote:
    > 
    > 
    >>Praveen,
    >>  This is a good question and has been raised before on the SI-LIST. 
    >>Serpentine etch is often done to match clock lines or source
syncronous 
    >>data lines.
    >>
    >>I did bench testing of serpentine lines, in conjuction with
simulations. 
    >>I ran SPICE simulations using field solved 2d models then measured 
    >>varying serpentine configurations. I examined impedance and
propagation 
    >>delay variations as a function of varying spacing, and signal edge
rate.
    >>
    >>When transmission lines are serpentined 'close' to themselves the 
    >>propagation delay decreases (The lines got faster). For example if I 
    >>compare a straight control line and a sepertined line of the same
length 
    >>on the same layer, with all the fixturing nulled the propagation delay

    >>went from 176ps/in (straight line) to 170 ps/inch (serpentined line). 
    >>You can think of the signal taking a shortcut across the distributed 
    >>self capacitance of the closely serpentined lines.
    >>You might think a propagation delay reduction is good, but I also
found 
    >>the variability of prop velocity increased. I believe the variability 
    >>increased because the capacitive coupling varies based on geometry, 
    >>while normally the dielectric constant variations are the only source
of 
    >>prop delay variability (for a specific rise time and frequency). The 
    >>variability is a small effect but is important when doing source 
    >>syncronous designs.
    >>
    >>
    >>Regards,
    >>Bob
    > 
    > 
    > 
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    -- 
    Robert J. Haller (rhaller@xxxxxxxxxx)
    Principal Consultant
    Signal Integrity Software Inc.
    6 Clock Tower Place, Suite 250
    Maynard, MA 01754
    Phone: (978) 461-0449, ext 15
    
    
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