[SI-LIST] Re: Series termination
- From: Vinayak AGRAWAL <vinayak.agrawal@xxxxxx>
- To: Vinayak <vinayak.agrawal@xxxxxx>, si-list <si-list@xxxxxxxxxxxxx>
- Date: Tue, 28 Dec 2004 14:59:21 +0530
Thanks Vinu and Patrick
Unfortunatly I have termination resistance specs and not return loss
specs. I'm not using a current steering topology and the termination
resistors are on-chip. The problem is that I'm an ASIC designer, I can
get package data but I don't have any experince of board design and I
don't know how to take board effects into account.
The output circuit may seem unusual but I don't think it is too unusual.
You can find something similar on page 91 of SATA (Serial ATA) 1.0a
specification (you can download from
http://www.serialata.org/docs/serialata10a.ZIP, or see the attached
page): there are two figures, first is a current steering driver (that
obviously has a parallel termination) and the second is similar to I'm
trying to design. This driver works effectively as two single-ended
drivers (properly synchronised to remove skew).
Another doubt I have is does 50ohm termination in a series-temrinated
single-ended driver really work as a 50ohm termination? Assuming signal
trace runs over a ground plane, then the return current for high speed
signals on this trace will run directly underneath the trace on the
ground plane, AND I ASSUME to the package and to the driver. But on a
high going transition the driver must get the return current through Vdd
(or Vtt). Which means it'll have to go through either the supply-ground
bypass capacitor or some other way. Either way there must be
siginificant inductances in the path (I'm sure I'm missing something,
but don't know exactly what) which means termination is not 50ohms, but
is 50ohms in series with an inductance (and may be some transmission
lines as well if the bypass capacitor is away from the chip). Will there
not be siginificant amount of reflections in such a case?
Regards
Vinayak
Vinu Arumugham wrote:
> While I am no expert, this looks like an unusual output structure.
> You may be familiar with the OIF CEI standard. These standards for
> 6/11 Gbps signaling, specify the common mode and differential return
> loss that TX and RX devices must meet with respect to ground. Most
> high speed differential interconnects at the system level are
> referenced only to ground. If your structure is able to meet
> specifications such as CEI, including package and package/board
> interface effects, they should be fine.
>
> Thanks,
> Vinu
>
>
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