[SI-LIST] Re: Serdes Tuning

  • From: Mervin Jacob <mervin.jacob@xxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 2 Feb 2015 17:11:45 +0530

Hi Bala,

I prefer to validate based on the few points,

1. The Material used for routing in terms of dissipation factor.
2. The width and length of the trace, Better to calculate the insertion 
loss. Specification says, insertion loss is approx. -14db
3. If you are using Xilinx device, use chipscope pro to find the eye and 
BER using loop back.


On 2/1/2015 7:23 AM, wh wrote:
>> Bala
>> You can test the traces with TDR from the via, and compare them. Another 
>> possibility is xtalk, especially Next, you can shut down the signal nearby 
>> the problem channels, and test again.
>> BR
>> 发自我的 iPad
>>
>>> 在 2015年1月31日,2:41,bala <balaseven@xxxxxxxxx> 写道:
>>>
>>> Hi Gert,
>>> We had done post layout channel analysis ,via,pad,anti pad size are
>>> optimized using 3D EM tool.Also only two channels are not working and other
>>> two are working fine though the channel loss,length ,via,pad,antipad,layer
>>> are same.All the channels were routed on top and bottom layer only,there is
>>> no via stubs.
>>>
>>> I sent 0101 clock pattern instead of actual random data pattern  and found
>>> eye was good with an extensive wide on working port and bad at non working
>>> port in the long run.
>>>
>>> Regards
>>> bala
>>>
>>>
>>> On Fri, Jan 30, 2015 at 9:42 PM, Havermann, Gert <Gert.Havermann@xxxxxxxxxxx
>>>> wrote:
>>>> Bala,
>>>>
>>>> If your Design followed all Design rules and was not simulated prior to
>>>> PCB Design, then it is very likely that you have an Return Loss Problem.
>>>> I'd expect a via Stub error. What is the via stublength and whats the
>>>> antipad size?
>>>> stublength exceeding 1mm and very small Antipads close youre eyes quickly
>>>> when there are also long traces.
>>>>
>>>> BR
>>>> Gert
>>>>
>>>>
>>>> ----------------------------------------
>>>> Absender ist HARTING Electronics GmbH, Marienwerderstraße 3, D-32339
>>>> Espelkamp; Registergericht: Amtsgericht Bad Oeynhausen; Register-Nr.: HRB
>>>> 8808; Vertretungsberechtigte Geschäftsführer: Dipl.-Kfm. Edgar-Peter
>>>> Düning, Dipl.-Ing. Torsten Ratzmann, Dipl.-Wirtschaftsing. Ralf Martin 
>>>> Klein
>>>>
>>>> -----Ursprüngliche Nachricht-----
>>>> Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>>> Im Auftrag von bala
>>>> Gesendet: Freitag, 30. Januar 2015 09:36
>>>> An: Boris Bakshan
>>>> Cc: si-list@xxxxxxxxxxxxx
>>>> Betreff: [SI-LIST] Re: Serdes Tuning
>>>>
>>>> Hi Boris,
>>>> The topology is like..FPGA-->XFI-->Phy-->SFI-->module.
>>>>
>>>> Regards
>>>> bala
>>>>
>>>> On Fri, Jan 30, 2015 at 12:11 PM, Boris Bakshan <bbakshan@xxxxxxxxx>
>>>> wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> Is it SFP+ links that you are trying to establish?
>>>>> It should comply with SFI and not XFI.
>>>>>> On Jan 29, 2015 8:24 PM, "I Nallathamby" <balaseven@xxxxxxxxx> wrote:
>>>>>>
>>>>>> Hi All,
>>>>>> I have four 10G SFP link in my design.Among four two are woking fine
>>>>>> even though the measured eye at the device pin violating the XFI
>>>>>> specification.However,other two ports are failing and the eye is
>>>>>> completely closed.The channel length,serdes setting,layer,trace
>>>>>> geometry are same for all the channels.Yet,only two ports are
>>>> failing,What could be the reason?
>>>>>> Regards
>>>>>> Bala
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>>>> --
>>>> bala
>>>>
>>>>
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>>>
>>> -- 
>>> bala
>>>
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