[SI-LIST] Re: Senior Signal Integrity Job opportunity - Position taken.
- From: "Ng, Kok SiangX" <kok.siangx.ng@xxxxxxxxx>
- To: "bkleveland@xxxxxxxxx" <bkleveland@xxxxxxxxx>, "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 24 Jun 2013 08:48:51 +0000
I am interested in Staff Validation Engineer (post-silicon) Opening which you
had mentioned below in your e-mail.
Is it during fall/2013 time frame? I also do have 5 years experiences in
PCB/Board design in the past employment with Intel and Altera.
Best Rgds,
Alex Ng
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Bendik Kleveland
Sent: Sunday, June 23, 2013 10:32 AM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: Senior Signal Integrity Job opportunity - Position taken.
Thanks all for your responses. We have currently signed a candidate for this
position, so please do not submit any more SI resumes.
We do still have the position open for the Staff Validation Engineer
(post-silicon). We are also considering an opening that is in the area of a
systems/board design in the fall/2013.
===========================================================
Hi,
The following job opportunity is in the approval process. I expect it to post
within a week. If you are interested, please contact me at bkleveland@xxxxxxxxx
- remove SI-LIST from the subject heading.
Thanks,
Bendik Kleveland
===========================================================
Job Description
Design and invent 56+ Gbps package and PCB board design for MoSys Bandwidth
Engine(r) and LineSpeed(tm) products. The responsibilities for the signal
integrity position are broad and unique as these new products are gaining
traction in the market. We are looking for someone who is capable of making a
huge impact over the next several years.
Responsibilities:
* Design and model high-end packages that are optimized for signal and
power integrity
* Design and model characterization boards, load boards, and system
level test boards
* Design of chip level RDL and bump map for optimum power distribution
and SI
* Direct s-parameter measurements with outside lab, correlate to
simulation and refine models
* Explore new solutions such as High Density Interconnects, Interposers,
and package-on-package (PoP)
* Interface with package, socket and PCB vendors
Desired Skills & Experience
* MS or Ph. D. in Electrical Engineering and 5+ years work experience
* Self-motivated with the ability to work well with others in a team
environment
* Experience with signal integrity design with emphasis on power and
signal distribution at PCB, packaging, and/or system level
* Experience with 3D modeling tools (HFSS, Power SI, ADS, Q3D) as well
as spice simulation tools
* Experience with laboratory measurements using equipment such as
oscilloscopes, vector network analyzers, spectrum analyzers
* Excellent analytical, design, and debug skills
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