[SI-LIST] Senior Signal Integrity Job opportunity

  • From: Bendik Kleveland <bkleveland@xxxxxxxxx>
  • To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Sat, 1 Jun 2013 17:27:36 -0700

The following job opportunity is in the approval process. I expect it to post 
within a week. If you are interested, please contact me at bkleveland@xxxxxxxxx 
- remove SI-LIST from the subject heading.
Bendik Kleveland

Job Description
Design and invent 56+ Gbps package and PCB board design for MoSys Bandwidth 
Engine(r) and LineSpeed(tm) products. The responsibilities for the signal 
integrity position are broad and unique as these new products are gaining 
traction in the market. We are looking for someone who is capable of making a 
huge impact over the next several years.
*       Design and model high-end packages that are optimized for signal and 
power integrity
*       Design and model  characterization boards, load boards, and system 
level test boards 
*       Design of chip level RDL and bump map for optimum power distribution 
and SI  
*       Direct s-parameter measurements with outside lab, correlate to 
simulation and  refine models
*       Explore new solutions such as High Density Interconnects, Interposers, 
and  package-on-package (PoP)
*       Interface with package, socket and PCB vendors

Desired Skills & Experience
*       MS or Ph. D. in Electrical Engineering and 5+ years work experience 
*       Self-motivated with the ability to work well with others in a team 
*       Experience with signal integrity design with emphasis on power and 
signal distribution at PCB, packaging, and/or system level
*       Experience with 3D modeling tools  (HFSS, Power SI, ADS, Q3D) as well 
as spice simulation tools
*       Experience with laboratory measurements using equipment such as 
oscilloscopes, vector network analyzers, spectrum analyzers 
*       Excellent analytical, design, and debug skills

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