[SI-LIST] Re: Self Impedance Analysis of Power Distribution Network
- From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
- To: balaseven@xxxxxxxxx
- Date: Tue, 27 Nov 2012 09:12:45 -0500
Bala,
Regarding the 100MHz frequency limit of capacitors: when people say this
they usually mean (or should mean) that maintaining approximately flat
impedance response beyond 100MHz just with discrete bypass capacitors
becomes very hard. The usual misconception is that people might think
based on the above statement that bypass capacitors cant do anything
useful above 100MHz. This is a plain wrong assumption. At very high
frequencies the PDN self impedance will be inductive anyway, so whether
you achieve the necessary low inductance from thin laminates or from a
combination of bypass capacitors or both, is up to the designer.
Regarding the bandwidth requirement: it always depends on the rise time
of the noise current hitting the particular PDN. And as such, it depends
on the location, even along the same PDN. A well-designed core or IO
PDN has the highest bandwidth near the silicon, lower in the package,
even lower on the board, and finally the lowest in the VRM.
The 50% current value for Ztarget calculation is not mandatory: if we know
the magnitude of the transient current, we should use that value. 50% is
a customary guess if there is no other data available.
Regards,
Istvan Novak
Oracle
On 11/27/2012 8:01 AM, bala wrote:
> *@ Siddharth Rajagopalan,
> *
> So if our impedance fails after 100MHZ,there is no point in changing PCB
> decoupling capacitors?We have to modify die-caps or package caps.Am i right?
> If the effect of ceramic capacitors on AC coupling will be upto 100
> MHZ,then we cannot modify the board decoupling for the IO frequency more
> than 100MHZ.
>
> *@ Experts talking about BANDWIDTH*
>
> Do we have to consider IO buffer's rise time or VRM's rise time?
>
> If we have to consider IO buffer's rise time,then what needs to be
> considered for core power supply?
>
> *@all,*
>
> Why we have to consider half a supply current for Ztarget calculation.
>
> Regards
> bala
>
>
> On Tue, Nov 27, 2012 at 12:03 PM, steve weir <weirsi@xxxxxxxxxx> wrote:
>
>> Sen, I think we've slipped a few decimal places here.
>> On 11/26/2012 10:13 PM, Sen Velmurugan wrote:
>>> Hi Bala
>>> Let me give you a perspective...
>>> For PDN modeled up to I/O die pads, band width of PDN is in the order of
>>> Mhz. Because PDN need to supply current for I/O banks at the rate of
>>> half clock rate in a worst case scenario.
>> If by MHz we can count to a thousand or more MHz, I am OK. If we are
>> talking about a few MHz, we are talking some really slow rise-times.
>>> For PDN modeled up to Package pads in the main PCB few Khz will be
>> enough.
>> This is highly package dependent. If the package and/or die does not
>> have substantial capacitance, then the device will be dependent on the
>> PCB PDN. This is not a problem when there are relatively few SSOs and
>> sufficient I/O Vdd and Vss connections to the PCB. It can and has been
>> a disaster for carelessly designed ASICs. There are many war stories
>> about such sad situations that no PCB design could fix. There is also
>> the flip-side where the ASIC design placed demands on the PCB that the
>> PCB designer ignored to their own peril.
>>> In the former case the caps on the package and other parasitic caps
>>> provide the instant current, in the later case on board HF caps and MF
>>> caps provide instant current.
>>> In your case, it looks like upto Package pads you need to do for few
>>> hundred KHz.
>> A few hundred KHz is an extremely low package cut-off usually reserved
>> for monster processor or GPU cores, not I/O.
>>> It depends on the di/dt requirement, the dt gives you the clue on how
>>> fast current you need to provide. This gives you the boundary of freq
>>> for which you need to ensure required low impedance. You can make it
>>> better if you can increase the boundary, but it may be costly or
>>> unnecessary.
>>> I hope you have good model of caps and parasitics of the PDN.
>>> ~Sen
>>>
>>> @Michael Greim I am considering PDN from source to PCB.I am okay with
>>> IR drop and density concept.. While doing Ac analysis(Self impedance vs
>>> Frequency) plot,i have no clue on upto what frequency it has to be
>>> done?Eric bogatin suggestive,it should be atleast 100MHZ for all PDN.For
>>> the device operating at KHZ frequencies,why should i have to run this
>>> upto 100MHZ? Say for example,I just wanted to know my self impedance
>>> curve of ARRIA-2's 2.5V LVCMOS supply which will consumes 2Amps
>>> maximum,and the operating frequency is 125MHZ.And my target impedance is
>>> 0.0625ohms..My question is;Should self impedance of my PDN be below this
>>> target impedance till 125MHZ?Why? Regards bala
>>>
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