Hi, guys Now I am studying the on-chip power grids scaling issue. It is claimed that the on-chip power grids is hard to scaled. Could someone give me a example to show what is the normal rule to caculate the scaling ratio of powr supply grid. For example, when we scale our technolgoy from .18um to .13 um, for the metal 6 which is used to implement power supply mesh, do we need to shrink the width, thickness and pitch of our power supply mesh? If so ( I believe so), what is the normal ratio? How does this ratio affect the RLC of power supply mesh? Thanks. Yiran Do you Yahoo!? Yahoo! Mail - More reliable, more storage, less spam ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu