[SI-LIST] Scaling effects on on-chip power grids

  • From: Yiran Chen <cyr_1976@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 18 Mar 2004 18:45:59 -0800 (PST)

Hi, guys
Now I am studying the on-chip power grids scaling issue. It is claimed that the 
on-chip power grids is hard to scaled. Could someone give me a example to show 
what is the normal rule to caculate the scaling ratio of powr supply grid. 
For example, when we scale our technolgoy from .18um to .13 um, for the metal 6 
which is used to implement power supply mesh, do we need to shrink the width, 
thickness and pitch of our power supply mesh? 
If so ( I believe so), what is the normal ratio? How does this ratio affect the 
RLC of power supply mesh?
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