[SI-LIST] Re: SSTL/DDR series termination
- From: "Novak David (TTE)" <david.novak@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 24 Oct 2005 08:59:16 -0500
Raj,
Have you created a design without any termination? I would be very
interested in knowing your experiences with such a design. I have been
very tempted to leave out all terminations, but I always chicken out due
to the overshoot specs. of typical micros.
I know of only two instances where large overshoots are allowed by the
spec. One is FPGA's and the other is DDR's. With that in mind, I
suspect that the design in the original question could be implemented
without any termination components, assuming the trace lengths are kept
very short.
David
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of raj singh
Sent: Sunday, October 23, 2005 8:45 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SSTL/DDR series termination
Ravinder,
One can make it work even without series termination for point2point
case, if your line is 50ohms, Driver is is also 50ohms. Please share
what issues you faced in this case.
Regards
Raj
--- Ravinder.Ajmani@xxxxxxxxxxxxxx wrote:
> Steve,
> You are right. There are differences between an ASIC and an FPGA. =20
> The point I was making was that a point-to-point SSTL/DDR interface=20
> can be implemented with series terminations only. The important thing
> is to simulate it thoroughly.
>=20
> Regards, Ravinder
> Server PCB Development
> Hitachi Global Storage Technologies
>=20
>=20
> Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
>=20
>=20
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> steve weir <weirsi@xxxxxxxxxx>
> 10/21/2005 11:47 AM
>=20
> To
> Ravinder.Ajmani@xxxxxxxxxxxxxx, Brad5m@xxxxxxx cc=20
> si-list@xxxxxxxxxxxxx Subject
> Re: [SI-LIST] Re: SSTL/DDR series termination
>=20
>=20
>=20
>=20
>=20
>=20
> Ravinder, Brad,
>=20
> An FPGA is likely to behave very differently from an
> ASIC for a number of=20
> reasons. What will work well varies depending on a
> number of factors=20
> including:
>=20
> FPGA family being used
> Data transfer rate
> I/O assignments
> DCI/ODT or not in the FPGA
> Board stack-up / power distribution
>=20
> Since Brad is new at this, I would get as much help
> as possible from your=20
> FPGA vendor. In all cases, simulation should be
> considered mandatory.
>=20
> Regards,
>=20
>=20
> Steve.
> At 09:06 AM 10/21/2005 -0700,
> Ravinder.Ajmani@xxxxxxxxxxxxxx wrote:
> >Hi Brad,
> >I have done a similar implementation in our design.
> In my case the
> >interface is between an ASIC and a single DDR chip,
> and the trace length
> >is about 2". The ASIC has 50 ohm drivers and the
> interconnects are also
> >designed for 50 ohm impedance. So I have placed
> series terminations on
> >Data and Strobe lines at the DRAM end only. After
> extensively simulating
> >the interface, I decided not to put any
> terminations on the Address and
> >Control lines. The differential clock has both
> series and parallel
> >terminations. I experienced cross-talk problem in
> the first board
> >revision, as I had not simulated for the worst case
> cross-talk. I have
> >had no problem with the interface since then.
> >
> >Recently I simulated the same topology for DDR2
> interface and it still
> >works quite well.
> >
> >Regards, Ravinder
> >Server PCB Development
> >Hitachi Global Storage Technologies
> >
> >Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
> >
> >
> >
> >Brad5m@xxxxxxx
> >Sent by: si-list-bounce@xxxxxxxxxxxxx
> >10/21/2005 08:41 AM
> >Please respond to
> >Brad5m@xxxxxxx
> >
> >
> >To
> >si-list@xxxxxxxxxxxxx
> >cc
> >
> >Subject
> >[SI-LIST] SSTL/DDR series termination
> >
> >
> >
> >
> >
> >
> >Hi all -
> >
> >This is my first time here -- please be gentle, and
> thanks for your help!
> >
> >I'm doing a design using a single 512Mb DDR2
> attached to an FPGA and I'm
> >entertaining the use of series termination for at
> least some of the
> >interface
> >between them, but still trying to convince myself
> that it will all work
> >OK. The
> >major impetus in using series term is that I could
> potentially entirely
> >lose
> >the Vtt supply, which would be highly desirable.
> The only thing *more*
> >desirable is that it all works when I'm done.
> >
> >The scheme is as follows:
> >-point-to-point connection between FPGA and DDR2
> >-trace lengths in the .75-1.25" range (a guess)
> >1) The unidirectional signals (e.g., address) from
> FPGA to DDR2 will be
> >"series terminated" by judicious setting of the
> FPGA output drive.
> >2) Same for the bidirectional signals (e.g., data)
> when driven by the
> >FPGA.
> >3) My 1st choice for managing the DDR=3D>FPGA data
> direction would be to
> >select a trace impedance that works well with one
> of the two available
> >DDR2 drive
> >strengths (maybe 75 ohms/reduced drive?). If that
> doesn't work, I could
> >presumably use resistors by the DDR to series
> terminate the "read"
> >direction.
> >
> >I have simulated the FPAG=3D>DDR2 direction, and with
> appropriate output
> >current settings on the FPGA it seems to look fine.
> It looks pretty much
> >just like
> >the parallel terminated (50-Vtt) case, only it has
> more amplitude. I
> >haven't
> >done the other direction yet (IBIS problem), but
> don't expect it to be
> >*too*
> >different since it is also an SSTL18 driver.
> >
> >The SSTL18 and DDR2 JEDEC specs contain a receiver
> parameter=20
> "Vswing(max)"
> >
> >that appears to say that signal amplitude must be
> no greater than 1Vpp.=20
> If
> >I am
> > reading that correctly, then it would appear that
> my series termination
> >scheme would violate the specs as it would
> generate > 1Vpp signals. Am I
> >reading
> >this correctly??
> >
> >So my questions are:
> >1) Any comments on Vswing(max)? Does it preclude
> the use of series
> >termination alone, or am I somehow reading it
> wrong? Any ideas of the
> >risks if I
> >ignore it??
> >2) Anyone else out there already done what I'm
> attempting to do here, and
> >want to tell me about it? I am especially
> interested in hearing comments
> >such as
> > "don't even think about it" or "no problem" --
> but only if they're=20
> true!
> >3) Any other comments/potential gotchas/etc.?
> >
> >The goal here, as always, is to have the simplest
> design possible, but no
> >simpler.
> >Thanking the DDR2/SSTL/SI experts in advance ...
> >Brad Cook
>=20
=3D=3D=3D message truncated =3D=3D=3D
=09
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