[SI-LIST] Re: SSTL termination resistor power
- From: "George Tang" <gtang@xxxxxxxx>
- To: "steve weir" <weirsi@xxxxxxxxxx>, <mike_bihan@xxxxxxxxxxxx>, "List` Si" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 26 Aug 2005 19:50:01 -0700
You are right. It does depend on a few factors. When the requirements are
met, it just works....
George
-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]
Sent: Friday, August 26, 2005 7:34 PM
To: gtang@xxxxxxxx; mike_bihan@xxxxxxxxxxxx; List` Si
Subject: Re: [SI-LIST] Re: SSTL termination resistor power
George that depends on a couple of factor. Dr. Johnson did a treatment on
this awhile back, and I believe he has one in his first book.
Steve.
At 03:52 PM 8/26/2005 -0700, George Tang wrote:
>Han,
>
>That (DC balance) is not a problem if you design it correctly. We run
>Gigabit PRBS data (non-DC-balanced) through AC coupling Caps all weeks
long.
>Actually, the whole industry does it.
>
>George
>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Bi Han
>Sent: Friday, August 26, 2005 9:05 AM
>To: George Tang; List` Si
>Subject: [SI-LIST] Re: SSTL termination resistor power
>
>
>Tang:
>
>Thanks for the information.
>
>One major problem with it, is the different termination impedance for DC-AC
>range. If the data is not well coded, like 8B/10B, then could cause
problem.
>
>Thanks again for the inputs.
>Han
>George Tang <gtang@xxxxxxxx> wrote:
>Han,
>
>I have not worked on DDR memory design for over 5 yrs, and I don't remember
>what we did before, so don't take my word for it. However, here is
>something to think about.
>Do an AC 60 ohm termination to gnd with a 1k pullup and 1k pulldown for the
>DC voltage bias.
>^
>|
>1K
>Driver -->-----------------|
>| |
>Z |
>| 1K
>= |
>| |
>V V
>
>
>George
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Bi Han
>Sent: Thursday, August 25, 2005 8:17 AM
>To: List` Si
>Subject: [SI-LIST] SSTL termination resistor power
>
>
>SSTL termination might use ODT termination for receiver side.
>
>The implementation is about 120ohm between PAD and VDDQ, another 120ohm
>between PAD and VSSQ. Overall AC impedance is about 60ohm.
>Since signal is DC coupled, there is DC current burning in terminaion
>resistors. If the PCB trace impedance is 60ohm, then the DC current in the
>termination resistor is about 20mA. It is so huge that I can not believe
>that DDR memory can afford it.
>
>Is there any way to reduce the power?
>
>thanks,
>Han
>
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