[SI-LIST] Re: SSTL_2 doubt
- From: raj singh <forsilist@xxxxxxxxx>
- To: starsilic@xxxxxxxxx
- Date: Mon, 18 Jun 2007 00:21:37 -0700 (PDT)
I always get confused with the ac level specs.
What was JEDEC intent behind including these levels in the spec?
From the JEDEC Standard documentation I understand that it is to take care of
ringing. This means it just to provied extra noise margin over dc levels.
Then why mem vendors spec timing with respect to ac levels? I have seen that
most of the receivers on these interfaces (HSTL, SSTL*) can switch with just
Vref +/-20,30mV of input swing. They need very small energy to switch. Much
lower than the area under 1V/ns slew and ac-levels.
Thanks and Regards
Raj
Kihong Kim <joshuakh@xxxxxxxxx> wrote:
I think you need to more specific to get the answer.
But by speculatioin....
If you are comparing DC specificaton to AC specification, you would not be
able to derive the numbers by simple math.
It is more like things regarding power applied to logic buffers AND signal
amplitude to logic threshold.
Kihong Joshua Kim
SI in Electronics and Photonics
On 6/15/07, Canes Venatici wrote:
>
> Hi,
> I'd gone through JEDEC SSTL_2 standard. In that I don't understand how
> Vih(ac) min is arrived at Vref+0.31v?
> The delta Vin min is given as 365mV. Then how the difference of 0.055v is
> accounted. I tried the noise on Vref may
> be imposed on 365mV, but that is just 25mV.
> Could anyone clarify it?
>
> Thanks
> Canes
>
>
>
>
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