[SI-LIST] Re: SSN Simulation
- From: steve weir <weirsi@xxxxxxxxxx>
- To: mohaghtalab@xxxxxxxxx
- Date: Sun, 06 Jan 2008 22:03:59 -0800
Mohamad, this may have changed, but the last time I checked Allegro had
problems with splits. You should check with your cadence FAE.
Steve
Mohamad Haghtalab wrote:
> Hi all
>
> I want to simulate my PCB for SSN,In Cadence Allegro(SI) I have problem
> with my DC shape ,in one layer I have more than one DC shape and for that
> cadence give me warning!
> what should i do for this problem?
> can suggest me another ways for simulating SSN (in board level)?
>
> Best Regards
>
> Haghtalab
>
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