Hi All,  Am running s-parameter model extraction for IC Packages.I have defined the port b/w Die Pin and Pkg Pin. It is for PCIE 2.0 Results helps to find out return loss, insertion loss and Xtalk of each Tx/Rx pair Now the query is, how to find the results are meeting  the spec or failing? If it is failing, what recommendation should be given to the Layout Engineers. That too esp for Insertion loss? and return loss.. Would appreciate kind response from you guys. Thanks RegardsKar ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List forum is accessible at: http://tech.groups.yahoo.com/group/si-list List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu