[SI-LIST] Re: [!! SPAM] Re: [SI-LIST]6 layers stackup - proof
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: Dan Smith <Dan.Smith@xxxxxxxxx>, Steve Weir <steve@xxxxxxxxxxxxx>, silist <si-list@xxxxxxxxxxxxx>
- Date: Wed, 27 Feb 2008 14:25:26 -0500
Dan,
We would be happy to discuss this with you off-line. However, you are
quite wrong, and thankfully your attachment was filtered by the Silist
software. PDS high frequency noise is proportional to the impedance at
the frequency being excited and the noise current being injected. So,
you are correct, it is Ohms Law. However, what you've forgotten is that
this is a complex impedance where
Z(f) = ESR + 1/(2 * pi * f * C) + 2 * pi * f * L
2-3 octaves above SRF this reduces to:
Z(f) = 2 * pi * f * L
For common high frequency bypass applications, the PDS is dominated by
capacitor body and mounting inductance above about 100 MHz. Some
capacitor mounting configurations are significantly (2x to 4x) better
than others.
best regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Dan Smith wrote:
> The x2y experiment compared 100nf x2y caps with 220nf 0402 caps. Note that=
> an x2y 200nf cap is really two 100nf caps from vcc to gnd. If the compari=
> son was 100nf x2y caps with 100nf 0402 caps the difference in noise between=
> the two experiments would have been negligible. That is my point so I dis=
> agree that my argument supports yours.
>
> dan
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On=
> Behalf Of steve weir
> Sent: Wednesday, February 27, 2008 10:33 AM
> To: Dan Smith
> Cc: Scott McMorrow; Lee Ritchey; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: [SI-LIST]6 layers stackup - proof
>
> Dan, actually you are making our point for us. A greater capacitance=3D20
> to inductance ratio makes for a wider bandwidth bypass cap that results=3D2=
> 0
> in lower noise. That is exactly what the X2Y(r) caps do, and is aptly=3D20
> demonstrated in the video.
>
> Regards,
>
>
> Steve.
> Dan Smith wrote:
>
>> All,
>> The howard johnson video had one fundamental flaw in how he (and steve)=
>>
> =3D
> came to their conlusion. This flaw was that the 0402 caps vs. the x2y c=
> =3D
> aps were not apples to apples comparisons. Why? The reason is comparing=
> =3D
> 0402 cpacitors of 220nf with x2y caps of 100nf are not the same thing! =
> =3D
> Sure, two 100nf caps in parallel equate to 200nf (which is what dr. johns=
> =3D
> on stated in the video as to why they are the same thing) but I challenge=
> =3D
> anyone to perform a noise experiment where you have 1 200nf cap vs. 2 10=
> =3D
> 0nf caps and try and get the same noise measurement. The resonance frequ=
> =3D
> ency of 200nf is about 16mhz and the resonance frequency of the 100nf is =
> =3D
> about 25mhz. thus the impedance due to these capacitors above 20mhz is g=
> =3D
> reater for the 200nf case - this is just fundamental capacitor science. =
> =3D
> This is exactly what happened in howard johnsons video. This is not rock=
> =3D
> et science just basic ohms-law. All this gobbly-gook talk of via incucta=
> =3D
> nce, etc. is in the small noise (no pun int
>
>> ended) of why the results in that video differed. See attachement.
>>
>> Dan
>>
>>
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx=
>>
> =3D
> ] On Behalf Of Scott McMorrow
>
>> Sent: Wednesday, February 27, 2008 9:34 AM
>> To: Lee Ritchey
>> Cc: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: [SI-LIST]6 layers stackup
>>
>> Lee
>> Fortunately for us, the physics are clear. If the correct land/via
>> patterns are used, 50 mils of via reach will not swamp out the
>> advantages of some types of low inductance capacitors. In fact, the
>> difference will asymptotically approach the inductance ratio of the
>> coupled via systems themselves at infinite via length.
>>
>> For the case of X2Y capacitors with 6-vias vs. 0402 with 4-vias, this
>> ratio is 2:1. That is, the 6-via pattern of the X2Y is 2 times as
>> efficient as the 4-via 0402 pattern. Even if we normalize for number o=
>>
> =3D
> f
>
>> vias, the X2Y pattern is still 1.33 times more efficient per via drill.=
>>
> =3D
>
>
>> However, in real PCBs we are not dealing with infinitely long vias, so
>> the performance advantage is much better, and typically 3:1 or 4:1
>> depending on the 0402 via pattern (2-via or 4-via) used.
>>
>> However, if you incorrectly design your board such that a PRF occurs
>> within a few octaves of where you need low PDS impedance, that is a
>> different issue altogether, which can only be resolved by moving the PR=
>>
> =3D
> F
>
>> with the correct spatial distribution of capacitors. Low inductance
>> capacitors are also more efficient in dealing with this problem.
>>
>>
>> Scott
>>
>> Scott McMorrow
>> Teraspeed Consulting Group LLC
>> 121 North River Drive
>> Narragansett, RI 02882
>> (401) 284-1827 Business
>> (401) 284-1840 Fax
>>
>> http://www.teraspeed.com
>>
>> Teraspeed(r) is the registered service mark of
>> Teraspeed Consulting Group LLC
>>
>>
>>
>> Lee Ritchey wrote:
>> =3D20
>>
>>> Tom,
>>>
>>> Well put!
>>>
>>>
>>>
>>> =3D20
>>>
>>>> [Original Message]
>>>> From: Tom Biggs <tbiggs@xxxxxxxxxxxxxxxxxxxxx>
>>>> To: <si-list@xxxxxxxxxxxxx>
>>>> Date: 2/26/2008 6:16:04 PM
>>>> Subject: [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup
>>>>
>>>> You can take the bulldozer analogy two ways. It depends on whether yo=
>>>>
> =3D
> u
>
>>>> care about the weight of the bulldozer with passengers, or just the
>>>> weight of the passengers.
>>>>
>>>> Steve's test fixture was geared toward 'weighing the passengers'. Lee=
>>>>
> =3D
> 's
>
>>>> was toward 'weighing the bulldozer'. So they each served their purpos=
>>>>
> =3D
> e.
>
>>>> His whole point was that the vias going down 50 mils on a board are
>>>> going to swamp out the advantages of low inductance caps. His test
>>>> fixture, by design, had vias that go down 50mils. I'm sure he'd agree=
>>>>
> =3D
>
>
>>>> that this would be a bad fixture for measuring the cap itself, which =
>>>>
> =3D
> was
>
>>>> not his goal.
>>>>
>>>> The appropriate land pattern to use for the low-inductance caps is a
>>>> separate issue. I'd be curious to see Lee's board with Steve's land
>>>> pattern.
>>>>
>>>> -tom
>>>>
>>>> -----Original Message-----
>>>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxx=
>>>>
> =3D
> rg]
>
>>>> On Behalf Of Muranyi, Arpad
>>>> Sent: Tuesday, February 26, 2008 1:31 PM
>>>> To: si-list@xxxxxxxxxxxxx
>>>> Subject: [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup
>>>>
>>>> Can't resist to illustrate this with an example:
>>>>
>>>> If you want to compare the weight of an ant and a cricket and you put=
>>>>
> =3D
>
>
>>>> them on top of the same bulldozer, you will not see much difference i=
>>>>
> =3D
> n
>
>>>> their weight...
>>>>
>>>> Arpad
>>>> ---------------------------------------------------------------------=
>>>>
> =3D
> ---
>
>>>> -----Original Message-----
>>>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxx=
>>>>
> =3D
> rg]
>
>>>> On Behalf Of Lee Ritchey
>>>> Sent: Tuesday, February 26, 2008 11:16 AM
>>>> To: Charles Grasso; Scott McMorrow
>>>> Cc: Steve Weir; QU Perry; si-list@xxxxxxxxxxxxx
>>>> Subject: [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup
>>>>
>>>> What does the test vehicle have to do with it? Both capacitors are
>>>> seeing
>>>> the same stackup. It's apples and apples. Why 26 layers? Lots of
>>>> PCBs
>>>> have 26 layers, pretty much all of them in terabit routers. This PCB=
>>>>
> =3D
>
>
>>>> was used to test may things besides these two capacitors.
>>>>
>>>> What is being presented is the difference between the two capacitors
>>>> under the same set of test conditions and it is not much.
>>>>
>>>> There are two sets of tests. One with the capacitors connected to th=
>>>>
> =3D
> e
>
>>>> first two planes inside the PCB, which is the lowest added inductance=
>>>>
> =3D
>
>
>>>> and the other is with the capacitors attached to two planes further d=
>>>>
> =3D
> own
>
>>>> in the PCB.
>>>> ------------------------------------------------------------------
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>>>> or to administer your membership from a web page, go to:
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>> -- Binary/unsupported file stripped by Ecartis --
>> -- Type: application/msword
>> -- File: X2Y_wool.doc
>> -- Desc: X2Y_wool.doc
>>
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>
>
> --=3D20
> Steve Weir
> Teraspeed Consulting Group LLC=3D20
> 121 North River Drive=3D20
> Narragansett, RI 02882=3D20
>
> California office
> (408) 884-3985 Business
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> Main office
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Other related posts:
- » [SI-LIST] Re: [!! SPAM] Re: [SI-LIST]6 layers stackup - proof
