[SI-LIST] Re: [SI-LIST]: Which tool is the best
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: "'arpad.muranyi@xxxxxxxxx'" <arpad.muranyi@xxxxxxxxx>,si-list@xxxxxxxxxxxxx
- Date: Wed, 5 May 2004 14:40:52 -0700
Arpad,
I'll take Kumar's advice, peace.
If your customer is happy with IBIS when you give them a choice of SPICE or
IBIS, good for you (BTW did you ever give them a choice ?).
If my customer is happy with SPICE when I give them a choice of SPICE or
IBIS, good for me, too.
Of course after Deng make his cat speech he send some tanks to kill a few
hundred people that disagreed with him so as long as both of us don't have
tanks, we'll be cool.
-----Original Message-----
From: C. Kumar [mailto:kumarchi@xxxxxxxxx]
Sent: Wednesday, May 05, 2004 3:57 AM
To: Chris.Cheng@xxxxxxxxxxxx; 'arpad.muranyi@xxxxxxxxx';
si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: [SI-LIST]: Which tool is the best
guys:
cool down - it is not religion!
"it does not matter whether it is a black cat or white cat as long as it
catches mice"
- Deng Psia Ping
=)
-----Original Message-----
From: Muranyi, Arpad [mailto:arpad.muranyi@xxxxxxxxx]
Sent: Wednesday, May 05, 2004 10:54 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [SI-LIST]: Which tool is the best
Chris,
To give you and the rest of the readers a little background and
history, I didn't "invent" IBIS so that I could go to exotic
places. I developed my first behavioral model using HSPICE's
controlled sources when my group was running the signal integrity
simulations for the very first (33 MHz) PCI bus. This was done
before anyone had a buffer design done, so the best we could do
was put together an IV curve and edge rate based behavioral model
to show that the reflected wave switching (and in those days we
also looked at the incident wave switching version) PCI bus will
work. And the reason this behavioral HSPICE model turned into the
IBIS specification was because this model was successful and there
was a great demand for it, even by our customers.
Regarding tweaking the design and the time it takes to convert to
IBIS, in my experience it was the other way around. We (the SI
team) would come up with the characteristics of the buffer using
behavioral models because it would be a lot easier to tweak the
IV curves, the edge rates, and the die capacitance values of the
behavioral model than keep tweaking the transistor parameters and
the circuit design, and we would then give the behavioral model to
the designers as a specification to be implemented in silicon.
Also, what I hear from various experienced engineers is that the
latest and greatest high speed buffers are becoming easier to
model (behaviorally) because they tend to be more linear than
ever before, and due to the high speeds they also have to be
kept simple.
By the way, there is a great deal of myth going around out there
about the accuracy of transistor level models. People tend to
think that it is the most accurate way of modeling circuits because
it has "all" the detail. The only thing they forget is that if they
don't have the correct process parameters and/or SPICE options,
they can get a lot of garbage. I have had this experience numerous
times. Even our design engineering team has been hurt by this=20
problem on more than just one occasion... So the great demand
you are referring to is not a proof for the goodness of SPICE
models. I am not saying this to put down SPICE, it has a lot
of merits, but people should not trust it as blindly as they do.
I have a question for you: Have you ever wondered whether we
should start using those models and simulators which are commonly
used by process design engineers? They do their work with even
more detail, involving quantum effects, crystal structures, doping,
electron mobility in the crystal, etc... If "more detail =3D higher
accuracy" is true, we should all start using these models for our
bleeding edge high speed buffers, instead of SPICE since SPICE is
just a behavioral abstraction of those..., correct? Hmmm... how
come we don't do it?
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
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