[SI-LIST] Re: [SI-LIST]: Distribution/Filtering/Decoupling Guide The 100Mhz clean cut off.

  • From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
  • To: "'epriest@xxxxxxxxxxxxxxxxxxx'" <epriest@xxxxxxxxxxxxxxxxxxx>,"'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 19 Jan 2004 12:57:58 -0800

I would sure like to know who would design their PLL VCO around the global
power distribution and not a dedicated power rail. 50mV of noise at the
right frequency can knock a VCO out of jitter spec but that among will be
more than acceptable for any global power spec. Don't mix apples with

-----Original Message-----
From: Ed Priest [mailto:epriest@xxxxxxxxxxxxxxxxxxx]
Sent: Monday, January 19, 2004 9:35 AM
To: Michael E. Vrbanac
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [SI-LIST]: Distribution/Filtering/Decoupling
Guide The 100Mhz clean cut off.

The scary comment wasn't about your proposal but it was about taking
data off of one design and applying it. You are trying to address this
problem by coming up with a method of finding out how power distribution
to and noise leaving uproc, FPGA, ASICs, different designs vary. I also
was not questioning other people's findings but I think that different
designs can have major differences. I have seen designs that break the
100Mhz cutoff (this problem can be exacerbated if you have VCO's or
resonances that are very sensitive to specific frequencies)

Any one who has been in the business any length of time has seen one of
the "rules" they came up with extended into places that no longer apply.
That was my concern here.

Mark said it well
"Based on that, we can intelligently evaluate our own=20
deviations from the standards". As long as this is done then we are

The process of coming up with a universal test platform is tough but it
is being done in 2nd level qual. issues and this will have a large
benefit but the amount of work to get there was fairly large. They had a
similar problem - all the chips could have vastly different


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