For starter I would like to subpena whoever propose these .8mm pin pitch package and put them in a public trial by their peers in Si-list and then hang them by high noon. What were they thinking ? Have they try to escape signals or deliver power to those package on a PCB ? -----Original Message----- From: steve weir [mailto:weirsp@xxxxxxxxxx] Sent: Friday, January 16, 2004 3:57 PM To: Chris.Cheng@xxxxxxxxxxxx; 'epriest@xxxxxxxxxxxxxxxxxxx' Cc: silist Subject: Re: [SI-LIST] Re: [SI-LIST]: Distribution/Filtering/Decoupling Gu ide The 100Mhz clean cut off. Chris, the intent is not to create a benchmark decoupling design. Far from it, it is an effort to create a method for specifying component power supply in a form that practical, by combining the component with its local attachment. If some chip manufacturer thinks they needs a zillion power / ground balls, then by specifying power as delivered into a ring on the power planes surrounding the part, the effect of carving up the planes is known. If they use fewer, then those effects are known as well. I think that it is pretty well demonstrated that at this stage of the game, the majority of integrators out there lack any or all: the chip data, tools, prowess to do the job that the really "big boys" can do from chip through system. Whether my idea is half-cocked or not, the effort is to be able to simplify the state-space so that with a competent understanding of impedance and cavity resonance ( whether by actual understanding or hand holding ), a PDS engineer can successfully integrate a given chip. Regards, Steve At 02:01 PM 1/16/2004 -0800, Chris Cheng wrote: >First, let me remind you of what I said below : > >"As a side note for those who want to built benchmark system design to >evaluate system to package distribution, good luck ! If you think you can >pick up something as subtle as the above, my hats off to you. I have enough >trouble doing a unique case where I know everything ahead of time." > >I don't believe in standards or references or papers or textbooks telling me >what I should do and what not. You come up with your own analysis based on >your own unique experiences and challenges. I suppose you have your own >experiences with >100W >GHz Si core power design and they may very well be >different from mine or Larry's situation. Most FPGA,ASIC or ASSP have lower >power and with lower core speed. But that doesn't mean they can get away >easy. > >If there is anything I said below I want you to take, it will be "do you own >analysis before drawing your conclusion". It is just an example of how over >design can cost you money but at the end of the day, a bad engineer under >design and his part fails. A good engineer over design and his part works. I >think I understand enough of Larry's company design methodologies (afterall, >I developed a lot of them) to say they don't throw pins in without reasons >but for every action you take, there is a consequence you pay. > >I don't understand what do you mean by "Increasing the inductance to the >board has a good chance of >increasing the coupling between different parts of the chips." Are you >suggesting someone is deliberately adding inductance to the board ? I am >not, neither is Larry. > >-----Original Message----- >From: Ed Priest [mailto:epriest@xxxxxxxxxxxxxxxxxxx] >Sent: Friday, January 16, 2004 10:07 AM >To: silist >Subject: [SI-LIST] Re: [SI-LIST]: Distribution/Filtering/Decoupling >Guide The 100Mhz clean cut off. > > >This is getting scary. Please do not globally take the number of >required power and grounds on a specific project and apply it to all >applications. Microprocessors, FPGA's, ASSP, ASICs all have a different >on chip environment. The amount of on chip capacitance, the closeness of >the di source to the chip capacitance, the presence of on chip mixed >signal IP, all could make reducing the number of power and grounds a bad >idea. Increasing the inductance to the board has a good chance of >increasing the coupling between different parts of the chips. Again, >microprocessors where both the circuits and power distribution are >custom designed can have a lot more friendly environment then other >chips you deal with.=20 > >This discussion and work can be very beneficial but applied incorrectly >can have disastrous effects. > >Ed > >-----Original Message----- >From: Ravinder.Ajmani@xxxxxxxx [mailto:Ravinder.Ajmani@xxxxxxxx]=20 >Sent: Friday, January 16, 2004 8:35 AM >To: Chris.Cheng@xxxxxxxxxxxx >Cc: silist >Subject: [SI-LIST] Re: [SI-LIST]: Distribution/Filtering/Decoupling >Guide The 100Mhz clean cut off. > >Chris, >Thanks a lot for the excellent explanation. Will you please tell me >what=20 >is the adequate number of power and ground pins for a 324 pin BGA >package.=20 > We use this package in two versions, C4 attach and wire bonded. >Regards, Ravinder >Server PCB Development >Hitachi Global Storage Technologies > >Email: Ravinder.Ajmani@xxxxxxxx > > > > >Chris Cheng <Chris.Cheng@xxxxxxxxxxxx> >Sent by: si-list-bounce@xxxxxxxxxxxxx >01/15/2004 06:56 PM >Please respond to Chris.Cheng > >=20 > To: "'Charles Grasso'" <cgrassosprint1@xxxxxxxxxxxxx>, Chris >Cheng=20 ><Chris.Cheng@xxxxxxxxxxxx>, "'Larry Smith'" <Larry.Smith@xxxxxxx> > cc: scott@xxxxxxxxxxxxx, silist <si-list@xxxxxxxxxxxxx> > From: si-list-bounce@xxxxxxxxxxxxx > Subject: [SI-LIST] Re: Distribution/Filtering/Decoupling >Guide The 100Mhz clean=20 >cutt off. > > > > >Well, I will give it a try based on what I now see as a complete picture > >of >what's going on with Larry's example. > >Disclaimer first >Since I was responsible for a lot of packaging and module designs in=20 >Larry's >company before I departed many years ago, I have to say I have never >seen=20 >or >reviewed or involved in any of the current or whatever future generation >package or module he is referring to. Everything I am saying is simply=20 >based >on what Larry has disclosed in this public forum. If my guess is wrong, >please accept my apology. > >To begin the discussion, I have to requote Zhiping's question below on >how >to "shift the power integrity problem to the PCB level". I claim there >is=20 >a >hard limit of 100MHz on the package power distribution, by that I mean=20 >with >the existing number of pins/sockets and package caps and on die=20 >decoupling, >all the available decoupling charge on the package and die will be=20 >consumed >and core voltage will start to drop after 10ns of continues current >drain=20 >on >die. Something on the PCB and external DC/DC regulator has to start >providing the charge to maintain the voltage level on die. By the same >token, due to the exiting impedance at the pins/socket and package, the >system (PCB or regulator) cannot reach the Si core power faster than=20 >100MHz. >This is based on an optimized pin analysis where I want to provide the=20 >least >amount of power and ground pins (if you ship a huge volume, like a 100M >of >them, @ a few cents per pin, you save a LOT of money) that can maintain=20 >the >minimum core noise level on die. The added benefit of it is you don't >need >to demand exotic >100MHz decoupling outside the package (since it won't=20 >help >anyways) and you also don't need to over kill your decoupling on package > >by >providing <100MHz decoupling bulk caps, just pass that responsibility to > >the >system folks. > >Now let's say you throw in too many power and ground pins on your >package. >Not only does it cost you money (@ a few cents per pin), it now also=20 >starts >to perforated your PCB power and gnd planes to the extend that the PCB >to >package impedance starts to pick up (shifting below 100MHz). Now you=20 >really >need to have a thin core PCB to lower the impedance back to equal the >case >when you have less power/ground pins with a smaller package. But in a=20 >sense, >this is exactly what Zhiping was asking for, shifting some of the=20 >integrity >problem to the PCB level. You can over design to an extend that what=20 >happen >in the PCB really start to impact the package performance.=20 > >It's your choice, too many pins and you will need BC and cost you >$$$$$$, >just enough pins and you don't need BC and save you some $ also. But if=20 >you >don't have enough pins, you are dead and no system or PCB design can >save >you. > >As a side note for those who want to built benchmark system design to >evaluate system to package distribution, good luck ! If you think you >can >pick up something as subtle as the above, my hats off to you. I have=20 >enough >trouble doing a unique case where I know everything ahead of time. > >Same old song here, there is no need for BC. Hey, that may be in my >second >broken record. > >-----Original Message----- >From: Charles Grasso [mailto:cgrassosprint1@xxxxxxxxxxxxx] >Sent: Thursday, January 15, 2004 5:34 PM >To: Chris.Cheng@xxxxxxxxxxxx; 'Larry Smith' >Cc: scott@xxxxxxxxxxxxx; silist >Subject: Distribution/Filtering/Decoupling Guide The 100Mhz clean cutt >off. > > >Chris, Larry et al... > >Can you please explain the 100MHz clean cut so often mentioned in ths >thread? Is it bandwidth (i.e related to rise time?) is it the crystal=20 >or... > >Puzzled. >Chas in Colorado.. > > >-----Original Message----- >From: zhiping yang [mailto:zhiping@xxxxxxxxx] >Sent: Tuesday, January 13, 2004 5:55 PM >To: Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx >Subject: Re: [SI-LIST] Re: Power Supply >Distribution/Filtering/Decoupling Guide] > > >Hi Chris, > >Thank you for sharing your thoughts and Very good points about the power >integrity. > >One comment about your "total system approach". Technically speaking, >it=20 >is >best to put the equal amount of efforts on the die, package and PCB >power >distribution since they are equally important in the complete power=20 >delivery >system. More important, the PCB COULD NOT fix the problems with the die > >and >package power delivery systems in some cases. > >In the real word, when cost and $$ is involved, the trade-offes must be >made, so the design may not be optimized in technical side. For >example, >due to the high cost of die size increase and package limitations, it >may=20 >be >more cost effective by shifting the power integrity problem to the PCB=20 >level >at a certain degree. This may require using BC or more decoupling caps >on >the board, but it could still be cost effective from the "total system" >point view. > >This is my $0.02 input. Thanks. > >Zhiping >------------------------------------------------------------------ >To unsubscribe from si-list: >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > >or to administer your membership from a web page, go to: >//www.freelists.org/webpage/si-list > >For help: >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > >List technical documents are available at: > http://www.si-list.org > >List archives are viewable at: > //www.freelists.org/archives/si-list >or at our remote archives: > http://groups.yahoo.com/group/si-list/messages >Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu