[SI-LIST] Re: SI models at MGH speeds
- From: "Kai Keskinen" <kalevi@xxxxxxxxxx>
- To: <sunil.mekad@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 26 May 2005 22:50:53 -0400
The problem with vendors giving you multi-GHz IBIS models is that accurate
differential logic models in IBIS such as CML require someone who really
understands both IBIS and SPICE to generate. Many of the IC vendors don't
want to spend the time (time=money) to learn how to do it right. I have some
good CML differential IBIS models from Intel that also tell you how to
implement pre-emphasis and they work in Cadence Allegro PCB SI. I haven't
seen anything comparable from other chip vendors.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of sunil.mekad@xxxxxxxxx
Sent: Thursday, May 26, 2005 12:06 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SI models at MGH speeds
Hi,
Can anyone tell me why it is difficult to generate IBIS models for
mutli-giga hz devices. Most of the vendors give us HSPICE models. Is it
something to do with difficulty in accurate characterisation of V/I
curve at such high frequencies (>5GHz)?
In any case are HSPICE models also the correct solution? Presuming such
interfaces also have pre-emphasis and de-emphasis. Cadence suggests the
use of macromodels for MGH applications however, is it possible to
convert HSPICE models to accurate macromodels for simulation in
SPECCTRAQUEST for >5GHz application?
Thanks
Sunil
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