[SI-LIST] SI Question 1 of 3: "Quiet" lines over split in ground plane
- From: "John-Paul Coetzee" <jpcoetzee@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 28 Oct 2005 18:25:15 +0100
I am working on a telecoms design with Analog and Digital areas. The =
whole unit is=20
inside a thick metal box, with the PCB bolted and grounded to the =
chassis across=20
the board. Various parts of the PCB are also further isolated by slots =
in the=20
ground and power planes and also by walls bolted to exposed ground plane =
on the top=20
and bottom of the board.
Here is an ASCII picture of small part of the board showing a digital =
area, analog=20
area, the slots isolating those areas and the soild metal wall. You will =
only be=20
able to see this picture properly in monospaced font
There are 3 SPI serial data and clock lines crossing into the analog =
zone. These=20
are only active in the first few seconds after power-up after which they =
are held=20
low.
What are the risks of these "quiet" signals crossing the slot?
| ######### D I G I T A L =
G R O U N D
| #########
| +---------+######### =
+--------------------------
| | |######### | =
=20
| | |######### | =
=20
| | |######### | S L =
O T =20
| | |### ### | =
=20
| | S |### W ### | =
=20
| | |### ### =
+--------------------------
| | L |### A ### =20
| | |### ###
| | O |### L ###
| | |### ###
| | T |### L ### A N A L O G =
G R O U N D
| | |### ###
| | |#########
| | |#########
| ------------------------#########------------->------- SPI Clock
| | |#########
| ------------------------#########------------->------- SPI Data
| | |#########
| ------------------------#########------------->------- SPI LE
| | |#########
| | |#########
| | |#########
| | |#########
| | |#########
| +---------+#########
| #########
| #########
| #########
+------------------------------------------------------------------------=
------------
--
JP Coetzee (was JP Nicholls) / jpcoetzee@xxxxxxxx =
<mailto:jpcoetzee@xxxxxxxx>=20
=20
Digital Design Engineer
=20
Powerwave UK Ltd
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