[SI-LIST] Re: SI Position Open
- From: "Joe Cahill" <jjcahill@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sat, 16 Jun 2001 09:13:57 -0500
Esther,
Your job description, job label, experience requirements are all fine a=
nd
accurate=2E I have been doing this kind of job since '82-'83=2E Even ba=
ck then
at the relatively slow signal data rates of 33Mbps and clock frequencie=
s of
33MHz understanding and controlling transmission line effects were
important for functioning systems=2E Also back then we were doing SSO
analysis and predictions, only we were arguing over 18->36 drivers
switching at a time, not several hundred=2E
This is not a resume and I am not interested in your position=2E I don'=
t have
a masters degree and I won't work in the Valley because my children may=
not
be able to earn enough to live there comfortably=2E
Joe
Enterprise Systems Card Development
Austin Phone: 512=2E838=2E6645
Rochester Phone: 507=2E253=2E0762 Fax: 507=2E253=2E4966
jjcahill@us=2Eibm=2Ecom
=
=20
esther williams =
=20
<estherw2000@yahoo To: si-list@freelists=2E=
org =20
=2Ecom> cc: =
=20
Sent by: Subject: [SI-LIST] SI =
Position Open =20
si-list-bounce@fre =
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elists=2Eorg =
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06/15/2001 05:04 =
=20
PM =
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Please respond to =
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si-list =
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Hello - The following is a SI position at an Optical Data Networking st=
art
up=2E
Please contact: Esther at ewilliams@photuris=2Ecom for more information=
=2E
Title: Senior Signal Integrity Engineer
Location: Mountain View, CA
Job Description:
- Specify, simulate, design and analyze high speed interfaces for data
networking systems=2E
- Verification of actual hardware and confirm the simulations results t=
o
guarantee integrity of all the high speed interfaces=2E
- Generate guide lines for board designers and layout designers for the=
high speed routing=2E
- Setup process to sign off layouts for PCB fabs=2E
Position Requirements:
- Experience with high speed IOs like LVDS, HSTL, SSTL, LVTTL, CML, PEC=
L=2E
- Familiar with high speed bus interfaces=2E
- Knowledgeable with ASIC design flow and IO selection process=2E
- Extensive use of SPICE and IBIS to simulate signal integrity for the =
high
speed board=2E
- Experience with QUAD like tools to sign off PCB layout designs=2E
- Multi-gigabit board design and EMI/EMC containment techniques=2E
- Defined impedance controlled PCB stack-ups and familiar with fabricat=
ion
process and backplane designs=2E
- MSEE or PhD=2E
- 8 + year's experience in signal integrity=2E
---------------------------------
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Yahoo! Buzz Index - Spot the hottest trends in music, movies,and more=2E=
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