[SI-LIST] Re: SI Engineer - Required in Force10 Networks - Chennai - India
- From: Heyfitch <heyfitch@xxxxxxxx>
- To: Saravana <saravana_force10@xxxxxxxxx>
- Date: Fri, 12 Nov 2010 10:18:19 -0800
Hello Saravana,
does Force10 cover relocation expenses (from the U.S. to Chennai)?
Best Regards,
Vadim
On Fri, Nov 12, 2010 at 2:12 AM, Saravana <saravana_force10@xxxxxxxxx>wrote:
> Hello SI Experts
>
> Force10 Networks India. is seeking a self-motivated individual that will be
> responsible for defining, developing, and analyzing hi-speed interfaces.
> Responsibilities will include board level SI design, backplane design,
> simulation, lab characterization, and verification. The ideal candidate will
> bring technical leadership and subject matter expertise along with extensive
> simulation and lab experience.
>
> Responsibilities:
> â?¢ Modeling hi-speed I/O's, printed circuit board interconnects, chip
> package, and connectors with respect to parameters such as loss,
> reflections, and crosstalk and designing to overcome these effects.
> â?¢ Contribute to the high speed signaling and interconnect technology
> selection
> Assess timing, noise margin, jitter, crosstalk, signal loss and signal
> integrity of all clocks and critical data signaling and develop noise
> analysis and timing budgets.
> â?¢ Design, tuning, and verification of HS serdes channels.
> â?¢ Review schematics and critical component specifications to provide
> feedback and recommendations.
> â?¢ Design of PCB stackups including material selections and geometry
> definitions.
> â?¢ Provide design constraints entry to PCB layout and perform post route
> simulations for timing and signal quality. Work with PCB designers to ensure
> proper implementation of all SI and EMI design requirements
> â?¢ Analyze, design, and verify PCB power distribution for noise suppression.
> â?¢ Take and correlate lab measurements to simulations. Create reports and
> detailed lab notes on analysis on measurement. Identify problems, analyze,
> and recommend solutions.
> â?¢ Support EE staff during board bringup and HW verification.
>
> Skills Experience Requirements:
> â?¢ Expert in hi-speed laboratory measurements techniques using the latest
> oscilloscopes, Vector Network Analyzers, Spectrum Analyzers, Time Domain
> Reflectometers and Bit Error Rate Testers.
> â?¢ Strong understanding of PCB layout principles including design for EMI
> and low noise power distribution. Familiar with PCB material properties.
> â?¢ Assess timing, noise margin, crosstalk, signal loss and signal integrity
> of all clocks and critical data signaling and develop noise and timing
> budgets
> â?¢ The candidate must have the expertise and experience to do channel
> analysis and familiar with advance behavior models (AMI) and must be capable
> of IBIS creation and verification as well have strong timing and signal
> integrity background especially in SDR, DDR, RDRAM and QDR interfaces.
> â?¢ Experienced with computer aided design tools such as Cadence
> Specctraquest, Mentor Graphics Hyperlynx, ICX, XTK. Experience with 3D
> modeling, HSPICE, APSIM, and IBIS modeling, signal integrity simulation
> HSPICE, and PCB layout (Allegro and Pads).
> â?¢ Excellent communication skills, both written and oral, as well as
> exceptional design organizational skills.
> â?¢ 5+ years of relative experience in signal integrity preferred.
>
> Location : Chennai - India
>
> Thanks
> SaravanaBhavan
> Staff Engineer
> Force10 Networks
> Mobile: +91-9840230903
> Skype: saravana_force10
> www.force10networks.com
>
>
>
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