[SI-LIST] SI Engineer Positions at EMC Corporation, Hopkinton, MA
- From: "arsenault, brian" <arsenault_brian@xxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 4 Aug 2004 11:34:06 -0400
There are currently two open positions within the Signal Integrity group
here at EMC Corporation. The two openings are for a Senior SI Engineer and
a Principal SI Engineer. I've included both descriptions and requirements
below.
These positions are in my group (Symmetrix Logic Engineering) and are
located in Hopkinton, MA (just west of Boston).
If you are interested or would like more information, please contact me
directly. Thanks!
Brian
Brian Arsenault
Principal SI Engineer
Symmetrix Logic Engineering
EMC Corporation
Hopkinton, MA 01748
arsenault_brian@xxxxxxx
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Senior SI Engineer
Description:
The ideal candidate should be one that can follow a product design from
conception, through simulation and lab bringup, all the way to release for
manufacturing. Work would involve, but is not limited to, buffer selection
and timing constraint development, board level pre- and post-route SI and
Timing, power delivery analysis and decoupling recommendation, model
validation and correlation, lab measurements in support of prototype
development, and working with board and chip designers to resolve issues
that may go beyond basic SI analysis.
Requirements:
- 3 to 6 years of related SI experience - board or chip design background
also a plus
- Knowledgeable in SpecctraQuest and HSpice - knowledge of SiAuditor and
Ansoft HFSS/SIWave a plus
- Experience with DDR, DDR2, PCI, PCI-X, PCI-Express, EIO, and other
multi-gigabit serial technologies
- Prior work on board level pre-route and post-route SI and Timing analysis
- Prior work with chip designers on buffer selection, model validation, and
lab experience
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Principal SI Engineer
Description:
Candidates should be comfortable working as a self-starter with little or no
direction. Work will include, but is not limited to, working with chip and
board designers on next-generation product development, model gathering and
validation, thorough SI and Timing analysis of board designs, working
directly with chip designers on buffer selection and timing constraint
development, lab debug and measurement support, and handling day-to-day
issues related to the project. Prior experience and future interest in
group leadership and management is preferred.
Requirements:
- 6 to 10 years of related SI experience - management/team leader experience
also a plus
- Knowledgeable in SpecctraQuest, HSpice, HFSS, and SIWave - SiAuditor
experience a plus
- Knowledgeable in DDR/DDR2/QDR memories, ASIC/FPGA SI analysis, PCI, PCI-X,
PCI-Express, EIO, SRIO, and other interface technologies
- Experience in working with chip and board designs on SI, Timing, and Power
Delivery modeling
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