[SI-LIST] Re: SERDES CDR with asynchronous reference clock?
- From: Leonard Dieguez <ldieguez@xxxxxxxxxx>
- To: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 10 Dec 2009 09:39:24 -0800
Ivor,
In the SERDES there is a PLL that will adjust the internal sampling clock
frequency. When there is no data or no lock the internal PLL will normally
frequency/ phase lock onto the reference clock. This frequency is typically
very close to the actual data rate. Once the receiver of the SERDES receives
data that data and the PLL clock is compared in frequency and phase in a
separate phase-frequency dectector (PFD) the error signal is then used to
adjust the PLL in such a way to sample the incoming data. In an analog system
quadrature PFD/sampling is used to align the data edge and the sampling edge to
the center of the data eye. Once the data is sampled it is then de-serialized
and passed as a word (normally a 10 bit word for 8B10B systems) to an elastic
buffer. The elastic buffer then will transfer the data into the local clock
domain like Steve Weir explains in his email.
This is a simplistic view and mainly an analog view. There are many other ways
to perform asynchronous sampling in the digital domain and at the higher speeds
half rate clocks are used. The above explanation is provided as a simple
conceptual view.
Leonard Dieguez
High Speed IO Applications,
Altera Corporation
9330 Scranton Road, Suite 400
San Diego, CA 92121
ldieguez@xxxxxxxxxx
858.202.3511 (office)
"There are two kinds of engineers - those who have signal integrity problems,
and those who will." - Eric Bogatin.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Bowden, Ivor
Sent: Thursday, December 10, 2009 12:31 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SERDES CDR with asynchronous reference clock?
Hi SI people,
Can someone offer an explanation how a SERDES CDR can recover data with an
asynchronous reference clock? Example is PCI-Express (reference PCI EXPRESS
BASE SPECIFICATION, REV 2.1 section 4.3.7.5. "Separate Refclk Architecture"),
where Refclk #1 drives the TX circuit and Refclk #2 drives the RX circuit. How
does this CDR circuit work? I thought that even if they were separate clocks
they'd have to be frequency locked, and a PCI-SIG presentation indicates they
can be +/-300ppm each.
Thanks,
Ivor Bowden
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