If you are seeing the ringing (glitch) at the package pin, check what it looks like at the die pad, if it's accessible in your simulation. Also take a look at the package model for the SDRAM controller (the load device). If it has a lot of inductance, you may get a glitch in the waveform at the IC pin, which is difficult to eliminate. But the waveform at the IC die pad may be clean. A small bit of capacitance at the load pin *might* reduce/eliminate the ringing, but might have undesirable results. Regards, Andy > I encountered SDR SDRAM data bus SI problem. From the simulation, I see a > serious ring during rising edge when source is SDRAM and the destination > is > SDRAM controller(point to point). The ring cause the data error in memroy > R/W operation. ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu