[SI-LIST] SDRAM connection topolgy on PCB

From: Sumathi Kuppuswamy <sumathi_ramana@xxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Fri, 13 Nov 2009 15:25:32 +0530 (IST)

Hi Experts,
In one of our design, we use 8 SDRAM to a processor.
We use Hyperlynx for SI simulation.
Address and control signals are connected to all SDRAMs in matched tree 
topology and they are good in simulation.
We face problems in data bits.

The data bus is shared by 2 SDRAMs, and there are totally 32 data bits.
We placed the SDRAMs on top and bottom to share the data bus with one via for 
each bit near SDRAMs.

There is a series termination near the processor for data bits.
When we simulated the data, write from processor is ok. But read from SDRAM has 
more ringing.

Other than tha above said tree topolgy, We tried the following methods.
1) Increasing the stub length in the above star toplogy
2) Daisy chain
3) Moved the series termination near SDRAM
4) Added series termination for each SDRAM
A) added parallel RC termination at SDRAM end
6) Added parallel resistor termination at SDRAM end.
All the above methods did work well.

I request any suggestion from you all.
Thanks
Sumathi


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[SI-LIST] SDRAM connection topolgy on PCB

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