[SI-LIST] Re: SDRAM bus termination
- From: "Martin Euredjian" <martin@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 1 May 2003 14:30:54 -0700
From: Mehrdad Salami
> SDRAM should work if FPGA have access to the same SDRAM clock. The
> other option is to provide clock from FPGA using PLL.
I've seen a Xilinx app note that describes the use of the DDR IO register
mechanism in order to deliver clocking that is in time with an outgoing data
bus. The idea is to use the very signal that clocks the data onto the
outgoing bus to generate an external clock as well. I haven't tried to
implement this yet but it's been in the back of my mind. I wonder, has
anyone in the list used this for SDRAM or other applications?
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
eCinema Systems, Inc.
voice: 661-305-9320
fax: 661-775-4876
martin@xxxxxxxxxxxxxx
ecinema@xxxxxxxx
www.ecinemasys.com
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