[SI-LIST] Re: SDRAM bus termination
- From: "Mehrdad Salami" <msalami@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 30 Apr 2003 09:39:57 +1000
SDRAM should work if FPGA have access to the same SDRAM clock. The other
option is to provide clock from FPGA using PLL. You can use the feedback
clock provided on some FPGAs to adjust the phases. Any difference between
FPGA clock and SDRAM clock will reduce the maximum clock frequency that
SDRAM work. This is situation if the data path from FPGA to SDRAM is short.
If the data path is long, the delay between data path between FPGA and SDRAM
should be equal to the delay between FPGA clock and SDRAM clock.
Mehrdad Salami
Hardware Design Engineer,
Colour Vision Systems,
================================
----- Original Message -----
From: "ganesancp" <ganesancp@xxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Wednesday, April 30, 2003 2:33 AM
Subject: [SI-LIST] SDRAM bus termination
>
> Hello SI experts,
>
> I am designing a board with one SDR SDRAM and i want to connect this
> SDRAM to a Xilinx Virtex-E FPGA in another board. SDRAM interface
> will be working at 120MHz and there is no other component in the bus
> (point-to-point).
>
> Any termination suggested for the data bus and any other SI related
> issues expected in this configuration?
>
> Regards,
> Ganesan
>
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