[SI-LIST] Re: SDRAM Termination
- From: "Dharmendra Gowra" <dharmendra.gowra@xxxxxxxxxxxx>
- To: <signalintegrity@xxxxxxxxxxx>, <saril_k@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 8 Jun 2006 09:55:54 +0530
Hi Saril and All,
If a 50E termination has to be put at the flash, I would recommend to
put the RC termination (to have less current assumption) where R will be
50E and the 'c' value to be decided by your data rate or speed.
Also it should be taken care of rise time of the signals(RC time
constant) which may lead to setup and hold timing violation.
Please correct me if I am wrong.
Thanks
Dharmendra.G
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Stephen Zinck
Sent: Wednesday, June 07, 2006 7:36 PM
To: saril_k@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SDRAM Termination
Hi Saril,
In my experience, I would put the SDRAM at the end of the line so
incident=20
wave switching occurs for this faster part (if you must daisy chain the=20
interface). The FLASH, because it is slower from a timing point of view,
can=20
easily handle the knee that will result (due to the fact that it is in
the=20
middle of the bus)... But I wouldn't forgo simulation. You still need to
understand if you have any signal integrity issues (no way to guess if
you=20
have a good termination methodology or not). You also need to find the=20
flight times associated with the paths to understand the resulting setup
and=20
hold margins. Signal integrity is important. But having the interface
work=20
in the lab/field from a timing point of view should always be highest on
the=20
triage list... You just can't do the timing analysis without simulation.
Best,
Steve
Stephen P. Zinck
Interconnect Engineering Inc.
P.O. Box 577
South Berwick, ME 03908
Phone - (207) 384-8280
Fax - (207) 676-8676
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com
----- Original Message -----=20
From: "Saril" <saril_k@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Wednesday, June 07, 2006 4:28 AM
Subject: [SI-LIST] SDRAM Termination
> Hi,
>
> We have an External Memory Interface Bus, which is shared by Boot
FLASH=20
> and SDRAM memories. This triggers a Daisy chain topology, we decided
to=20
> use a 33 ohm series termination resistor near to the CPU bga balls and
> route to SDRAM first, then take it to the FLASH. But there is one more
> suggestion, put a 50ohm parallel termination ( trace impedance is 50
ohm)=20
> to ground at the end of the trace near to FLASH, but it will consume
more=20
> current.
>
> Can anybody please give a good termination strategy for this Daisy
chain=20
> topology?
>
> Thanks and regards
> Saril Kaiprath
> Design Engineer
> FDL
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>=20
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