[SI-LIST] Re: SDRAM Termination
- From: "Stephen Zinck" <signalintegrity@xxxxxxxxxxx>
- To: <saril_k@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 7 Jun 2006 10:05:38 -0400
Hi Saril,
In my experience, I would put the SDRAM at the end of the line so incident
wave switching occurs for this faster part (if you must daisy chain the
interface). The FLASH, because it is slower from a timing point of view, can
easily handle the knee that will result (due to the fact that it is in the
middle of the bus)... But I wouldn't forgo simulation. You still need to
understand if you have any signal integrity issues (no way to guess if you
have a good termination methodology or not). You also need to find the
flight times associated with the paths to understand the resulting setup and
hold margins. Signal integrity is important. But having the interface work
in the lab/field from a timing point of view should always be highest on the
triage list... You just can't do the timing analysis without simulation.
Best,
Steve
Stephen P. Zinck
Interconnect Engineering Inc.
P.O. Box 577
South Berwick, ME 03908
Phone - (207) 384-8280
Fax - (207) 676-8676
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com
----- Original Message -----
From: "Saril" <saril_k@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Wednesday, June 07, 2006 4:28 AM
Subject: [SI-LIST] SDRAM Termination
> Hi,
>
> We have an External Memory Interface Bus, which is shared by Boot FLASH
> and SDRAM memories. This triggers a Daisy chain topology, we decided to
> use a 33 ohm series termination resistor near to the CPU bga balls and
> route to SDRAM first, then take it to the FLASH. But there is one more
> suggestion, put a 50ohm parallel termination ( trace impedance is 50 ohm)
> to ground at the end of the trace near to FLASH, but it will consume more
> current.
>
> Can anybody please give a good termination strategy for this Daisy chain
> topology?
>
> Thanks and regards
> Saril Kaiprath
> Design Engineer
> FDL
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